Tag: FOSSi

SiFive Freedom E310 processor

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

RISC-V Workshop Logo

RISC-V Workshop Taiwan Slides Now Available

The RISC-V Foundation has published slides from the RISC-V Workshop Taiwan, which took place earlier this month as a means of showcasing the ecosystem and highlighting both ongoing and future projects. “RISC-V Workshop Taiwan showcased the open, expansive and international RISC-V ecosystem, highlighting current and prospective projects and implementations that… Read More
Microsoft Project Zipline

Microsoft Opens Zipline Hardware-Implementable Compression Algorithm

Microsoft’s cloud computing division, Azure, has announced the release of its hardware-implementable compression algorithm Project Zipline under a permissive licence, as part of the Open Compute project (OCP). “Microsoft’s Project Zipline compression algorithm yields dramatically better results, up to 2X high compression ratios versus the commonly used Zlib-L4 64KB model,”… Read More
Calista Redmond

Calista Redmond Named as RISC-V Foundation CEO

The RISC-V Foundation has announced the appointment of IBM alumnus Calista Redmond as chief executive officer, taking over from interim chief Martin Fink. Calista Redmond’s work history includes 20 years of senior-level management and alliance experience at companies including Affinity Lab and Articulated Impact, including 12 years at IBM where… Read More
SiFive HiFive1 MCU (Cropped)

Amazon Adds RISC-V Support to FreeRTOS Kernel

Amazon has announced that it has added support for the RISC-V open instruction set architecture (ISA) to the MIT-licensed FreeRTOS real-time operating system kernel. “RISC-V is a free and open ISA that was designed to be simple, extensible, and easy to implement. The simplicity of the RISC-V model, coupled with… Read More