Author: Gareth Halfacree

Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.

QEMU 4.1.0 Extends RISC-V Open ISA Support

The open-source QEMU machine emulator and virtualiser has received enhanced support for the open RISC-V instruction set architecture (ISA) in its 4.1.0 release. Following on from the 4.0.0 release back in April, QEMU 4.1.0 brings a range of improvements to its support for the open RISC-V ISA. Chief among… Read More

Researchers Publish Roadmap for RISC-V Opportunities in Space Tech

Researchers at the Delft University of Technology have published a roadmap which seeks to maximise the potential of the open RISC-V instruction set architecture (ISA) for space applications across the full range of requirements from low-power microcontrollers up to high-end payload processors for artificial intelligence applications. “This paper proposes a… Read More

CHIPS Alliance Launches FuseSoC-Based SweRVolf System on Chip Design

CHIPS Alliance has launched a system-on-chip (SoC), built using Western Digital’s open-source SweRV Core and the FuseSoC build toolset, dubbed SweRVolf A collaboration between FuseSoC creator and maintainer Olof Kindgren, Western Digital Director of Next Gen Platforms Tech Zvonimir Bandic, outgoing chief technology officer Martin Fink, and CHIPS Alliance, SweRVolf… Read More

FSFE Launches REUSE 3.0 Licence Compliance Specification, Support Tool

The Free Software Foundation Europe (FSFE) has announced the release of REUSE 3.0, a copyright and licensing specification and supporting utility designed to make license compliance as simple as possible for free and open source projects. “The licensing of a software project is critical information,” explains FSFE’s Carmen Bianca Bakker… Read More

Andes Technology Points to Explosive RISC-V Growth

Andes Technology has announced explosive demand for its proprietary processor cores based on the open RISC-V instruction set architecture (ISA), highlighting the growing demand for alternatives to x86, Arm, MIPS, and other proprietary ISAs. Born from the University of California at Berkeley in 2010, the open RISC-V instruction set architecture… Read More

The Things Network, Servet Balloon Launch 2019

The Things Network Sets New LoRaWAN Transmission Record

The Things Network, the community-driven LoRaWAN project, has announced a world record successful transmission distance from the Servet project: 476 miles, or 766 kilometres. Designed for low power yet wide area use, LoRaWAN is the technology behind community-driven wide-area networking project The Things Network – the largest open LoRaWAN network… Read More

Alibaba Unveils High-Performance 16-Core 2.5GHz RISC-V Chip Design

Alibaba, via the Pingtouge (T-Head) division of its DAMO Academy, has announced what it claims is the world’s most powerful processor based on the open RISC-V instruction set architecture (ISA): a 16-core 2.5GHz design built on a 12nm process node, dubbed the CoreXuanTie910 or XT910. “The breakthrough is more than… Read More

CRU: RISC-V Soft-Core Contest, Wuthering Bytes Programme, Plan 9 for Raspberry Pi, and More

The RISC-V Foundation, in partnership with Microchip Technology and Thales, has announced its second soft-core CPU competition – time time focusing on security. Following on from its first soft-core CPU contest late last year, the RISC-V Foundation has announced its second. Where the first focused on performance and smart… Read More

PULP Platform Tapes Out Urania Heterogeneous RISC-V ASIC

The Parallel Ultra-Low Power (PULP) Platform project has announced tape-out of Urania, an implementation of its bigPULP design which combines one Ariane core with two quad-core RISC-V clusters. Announced back in February last year, Ariane is a 64-bit application-class RISC-V core design, created as a joint effort between ETH… Read More

Microchip Shows Off Rad-Hardened RISC-V for Low-Cost Satellites

Microchip’s Dorian Johnson has penned a piece on the open RISC-V instruction set architecture (ISA)’s ascent into space, courtesy of radiation-hardened implementations from his company. “Using the new open RISC-V architecture, the FPGA circuitry can operate advantageously close to a remote measurement source,” Johnson explains in the piece for Elektroniikkalehti. Read More

Pepijn de Vos's 7400-series Breathing Circuit

Pepijn de Vos’ 74-Series Project Goes Straight from VHDL to PCB

Engineer Pepijn de Vos has released the source code and video demonstration for a five-chip 74-series logic gate ‘breathing LED circuit’ – without ever having had to manually design the printed circuit board. “I had been keeping an eye on Yosys, the open source HDL synthesis tool, which can apparently… Read More

Plan 9 from Bell Labs Gets Early Support for the Raspberry Pi 4

An effort to port the Plan 9 from Bell Labs operating system to the Raspberry Pi family of low-cost single-board computers has received initial support for the new Raspberry Pi 4 – though there’s still work to do on the project. First released in 1992 for academic users and 1995… Read More