Author: Gareth Halfacree

Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.

Wave Computing Announces MIPS Open Initiative

Wave Computing has announced the MIPS Open initiative, under which it plans to make the instruction set architecture (ISA) available free of charge with no licensing or royalty payments required – a clear response to the growing popularity of the open RISC-V ISA. Wave Computing, which acquired MIPS from Imagination… Read More

Bluespec Launches Commercially-Supported Flute RISC-V Cores

RISC-V specialist Bluespec Inc. has announced its second RISC-V processor design, Flute, which it is making available as basic cores ahead of future releases which will include additional instructions for Linux and FreeRTOS compatibility. The follow-up to Bluespec’s existing Piccolo core, Flute is currently available in RV32IMU and RV64IMASU implementations… Read More

CRU: Free RISC-V Boards, Security in the FOSSi Era, and More

OpenISA has officially launched the VEGAboard microcontroller development board, based on the PULP Platform’s RI5CY and Zero-RI5CY RISC-V core, and it’s giving them away to encourage adoption of the free instruction set architecture (ISA). Developed in partnership with the Parallel Ultra Low Power (PULP) Platform, Express Logic, Foundries.io, Ashling, IAR… Read More

Round-Table Discusses RISC-V, FOSSi Impact on Hardware Security

Semiconductor Engineering’s Ed Sperling has published extracts of a round-table with Rambus’ Helena Handschuh, Microsemi’s Richard Newell, and Galois’ Joseph Kiniry on the impact the open RISC-V instruction set architecture (ISA) can have on security. “With open source, you have the opportunity to review it and come up with comments,… Read More

Joint Development Foundation Joins Linux Foundation for Easier Standardisation

The Linux Foundation has announced that it is bringing the Joint Development Foundation under its wing, in order to bring together open source and open standards development and simplify the route to standardisation for developers. The partnership between the two organisations will, they claim, benefit both individual open-source developers and… Read More

Tom Verbeure on the VexRiscV CPU: “A New Way to Design”

Engineer Tom Verbeure has written up an analysis of the VexRiscV CPU, a RISC-V design implemented using the novel SpinalHDL hardware description language (HDL) – an approach he describes as being “as efficient as the most optimised Verilog, yet at the same time extremely configurable.” First-prize winner in the recent… Read More

Microsemi, SiFive Launch Linux-Compatible RISC-V PolarFire SoC

Microsemi has announced a new system-on-chip (SoC) architecture which combines the company’s PolarFire low-power field-programmable gate arrays (FPGAs) with a complete RISC-V processor implementation for use with Linux platforms. Developed in partnership with RISC-V pioneer SiFive, the PolarFire SoC includes an asymmetric coherent CPU cluster with four 64-bit RV64GC RISC-V… Read More

Western Digital Unveils Open SweRV RISC-V Core

Western Digital has unveiled its first in-house RISC-V core, dubbed SweRV, and it has confirmed plans to release it under an open source licence early next year. Part of a company initiative, started in 2017, to switch from proprietary instruction set architectures (ISAs) to the open RISC-V ISA across its… Read More

PULP, OpenPiton Partner on OpenPiton+Ariane Design

The OpenPiton project has announced a partnership with the PULP Platform to combine the OpenPiton open-source research processor platform with the 64-bit Ariane RISC-V core, creating what is described as “the ideal permissive open-source RISC-V system.” The Parallel Ultra Low Power (PULP) Platform announced Ariane, a 64-bit application-class RISC-V design,… Read More

OpenISA Launches New, Free RISC-V VEGAboard

SiFive HiFive1 Board, Courtesy of SiFive

CRU: RISC-V Growth, Transprecision Funding, Reverse-Engineering, and More

Princeton University’s OpenPiton free and open source silicon (FOSSi) project has announced what is claimed to be the world’s first open-source, general-purpose, heterogeneous-ISA processor: JuxtaPiton. Built by combining the SPARC v9-based OpenPiton with Clifford Wolf’s PicoRV32 RISC-V core, JuxtaPiton is something unique. “JuxtaPiton inherits all of the capabilities of OpenPiton,… Read More

JEDEC to Release 3D Component Models Alongside 2D Drawings

Microelectronics industry standards organisation JEDEC has announced that it plans to release 3D models of new standard modules, packages, and socket outlines, in addition to the traditional 2D drawings it provides. “The demand for 3D models in electronics design and manufacturing is set to grow exponentially with the expansion of… Read More