Author: Gareth Halfacree

Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.

Google Launches Coral Edge TPU Development Board, USB Accelerator

Google has announced it is bringing its Tensor Processing Unit (TPU) technology to external developers for the first time, launching a suite of development boards and accelerators for edge-processing under the Coral brand. Google first announced the Tensor Processing Unit, an in-house custom silicon project to accelerate deep-learning compute performance… Read More

FuseSoC 1.9.1 Brings Improved, Sphinx-Generated Documentation

Olof Kindgren has announced the release of FuseSoC 1.9.1, and it brings with it improved documentation produced using the Sphinx Python Documentation Generator. Having a useful end product should be the primary goal of all open-source projects, but it shouldn’t be viewed as the only goal: no matter how useful… Read More

Linux Kernel 5.0 Launches with New RISC-V Features, Fixes

Linus Torvalds has announced the release of Linux 5.0, the latest version of the Linux kernel, and once again it pulls in a range of improvements and new features for the RISC-V instruction set architecture (ISA). Linux has boasted support for the open RISC-V ISA for a while, now, to… Read More

FOSSi Foundation Selected as Google Summer of Code Mentor Organisation

The Free and Open Source Silicon (FOSSi) Foundation has announced it has been selected once again to be a mentor organisation in the Google Summer of Code (GSoC) programme, and is looking for students to participate. A not-for-profit organisation founded with the aim of promoting and assisting with the development… Read More

Amazon Adds RISC-V Support to FreeRTOS Kernel

Amazon has announced that it has added support for the RISC-V open instruction set architecture (ISA) to the MIT-licensed FreeRTOS real-time operating system kernel. “RISC-V is a free and open ISA that was designed to be simple, extensible, and easy to implement. The simplicity of the RISC-V model, coupled with… Read More

Imagination, Andes Partner on Wireless RISC-V Microcontroller Product

Imagination Technologies and Andes Technology have announced a partnership to combine the former’s Ensigma wireless intellectual property (IP) with the latter’s RISC-V N22 microcontroller IP in order to create an off-the-shelf product aimed at the Internet of Things (IoT) sector. The collaboration between the two companies marks the first time… Read More

GreenWaves’ €7m Series A Round Shows Hunger for RISC-V, FOSSi

GreenWaves Technologies, which launched the GAP8 RISC-V low-power processor and GAPuino development board in February last year, has announced that it has raised €7 million in Series A funding – a clear demonstration of the startling growth in the free and open source silicon (FOSSi) market. “This support from… Read More

CRU: Open ISA Events, New RISC-V & LoRaWAN Parts, IoT Regulation, and More

AB Open’s Andrew Back has published a piece on building a personal computer based on the RISC-V instruction set architecture (ISA), using a custom-designed housing containing a SiFive HiFive Unleashed development board and Microsemi Expansion Board. “While it’s clear that the most significant opportunities for RISC-V will be in democratising… Read More

DVCon 2019 to Host Panel Discussion on Open ISAs’ Impact on Verification and Compliance

The Design and Verification Conference (DVCon) 2019 is to host a panel on the verification and compliance implications of open instruction set architectures (ISAs) like RISC-V, organised by industry expert Imperas. Dubbed “Verification and Compliance in the Era of Open ISA – Is the Industry Ready to Address the Coming… Read More

RISC-V Workshop Zurich Call for Speakers Now Open

The RISC-V Foundation has issued a call for speakers ahead of the RISC-V Workshop Zurich, scheduled for mid-June 2019, with a submission deadline of the 28th of February. Hosted by the non-profit RISC-V Foundation in partnership with Informa’s Knowledge & Networking Division, KNect365, the RISC-V Workshop Zurich is to be… Read More

WCH Adds Upcoming RISC-V Bluetooth LE Microcontroller to CH57x Family

Embedded news site CNXSoft has highlighted an upcoming part from Jiangsu Qinheng Co., Ltd, also known as WinChipHead (WCH), which combines a RISC-V core running at 60MHz with Bluetooth Low Energy (BLE) connectivity. Recently added to WCH’s parts list, the 32-bit microcontroller has been dubbed the CH572 – putting it… Read More

Seeed Studio Stocks Sub-$18 RISC-V Sipeed Tang Primer FPGA Board

Internet of Things (IoT)-focused components provider Seeed Studio has begun stocking the Sipeed Tang Primer FPGA development board, a sub-$18 part which features an Anlogic EG4S20 FPGA running a RISC-V soft core. Designed to offer a full RISC-V implementation in a very small form factor, the Tang is based around… Read More