Tag: RISC-V

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

Western Digital Releases SweRV RISC-V Core Source Code

Storage giant Western Digital has officially released the source code for its SweRV RISC-V core, under the permissive Apache 2.0 Licence, allowing anyone to run, experiment with, or modify its implementation. Announced back in December, SweRV is a RISC-V core implementation developed in-house as part of Western Digital’s aim… Read More

SiFive HiFive1 Board, Courtesy of SiFive

CRU: RISC-V’s Bumper Year, LoRaWAN Growth, cocotb 1.1, and More

The RISC-V Foundation has released a video highlighting some of the key features of the 2018 RISC-V Summit, held in Santa Clara late last year and attended by over 1,100 community members. To say that the free and open source silicon (FOSSi) movement in general and RISC-V in particular had… Read More

Thales, IIT Madras Partner for Fault-Tolerant SHAKTI RISC-V Processors

Thales, which recently became a member of the RISC-V Foundation, has announced a joint project with IIT Madras to develop a fault-tolerant version of the SHAKTI Project RISC-V CPU. “After the two successful fabrication and booting of SHAKTI with two technology nodes, 22nm (Intel Fab, Oregon USA) and 180nm… Read More

Bluespec Launches Commercially-Supported Flute RISC-V Cores

RISC-V specialist Bluespec Inc. has announced its second RISC-V processor design, Flute, which it is making available as basic cores ahead of future releases which will include additional instructions for Linux and FreeRTOS compatibility. The follow-up to Bluespec’s existing Piccolo core, Flute is currently available in RV32IMU and RV64IMASU implementations… Read More

CRU: Free RISC-V Boards, Security in the FOSSi Era, and More

OpenISA has officially launched the VEGAboard microcontroller development board, based on the PULP Platform’s RI5CY and Zero-RI5CY RISC-V core, and it’s giving them away to encourage adoption of the free instruction set architecture (ISA). Developed in partnership with the Parallel Ultra Low Power (PULP) Platform, Express Logic, Foundries.io, Ashling, IAR… Read More

Round-Table Discusses RISC-V, FOSSi Impact on Hardware Security

Semiconductor Engineering’s Ed Sperling has published extracts of a round-table with Rambus’ Helena Handschuh, Microsemi’s Richard Newell, and Galois’ Joseph Kiniry on the impact the open RISC-V instruction set architecture (ISA) can have on security. “With open source, you have the opportunity to review it and come up with comments,… Read More

Microsemi, SiFive Launch Linux-Compatible RISC-V PolarFire SoC

Microsemi has announced a new system-on-chip (SoC) architecture which combines the company’s PolarFire low-power field-programmable gate arrays (FPGAs) with a complete RISC-V processor implementation for use with Linux platforms. Developed in partnership with RISC-V pioneer SiFive, the PolarFire SoC includes an asymmetric coherent CPU cluster with four 64-bit RV64GC RISC-V… Read More

Western Digital Unveils Open SweRV RISC-V Core

Western Digital has unveiled its first in-house RISC-V core, dubbed SweRV, and it has confirmed plans to release it under an open source licence early next year. Part of a company initiative, started in 2017, to switch from proprietary instruction set architectures (ISAs) to the open RISC-V ISA across its… Read More

PULP, OpenPiton Partner on OpenPiton+Ariane Design

The OpenPiton project has announced a partnership with the PULP Platform to combine the OpenPiton open-source research processor platform with the 64-bit Ariane RISC-V core, creating what is described as “the ideal permissive open-source RISC-V system.” The Parallel Ultra Low Power (PULP) Platform announced Ariane, a 64-bit application-class RISC-V design,… Read More

OpenISA Launches New, Free RISC-V VEGAboard

Sipeed Launches Crowdfunder for RISC-V MAIX AI Dev Boards

Chinese electronics company Sipeed has launched a crowdfunding campaign for a range of development boards based on a Kendryte K210 dual-core 64-bit RISC-V processor, aiming to bring artificial intelligence (AI) processing to edge devices and with pricing starting at $5 per board. “Sipeed MAIX is the first RV64 AI board… Read More

Embecosm's Buildroot RISC-V Patch Set in Action

Embecosm’s Mark Corbin Adds RISC-V Support to Buildroot

Buildroot, a tool for easily generating complete Linux system images for embedded platforms through cross-compilation, has announced official support for the open RISC-V instruction set architecture following the merging of a patch set by Embecosm’s Mark Corbin. Merged into the Buildroot source this weekend, as confirmed on the project’s… Read More