Tag: Embedded

Get the latest news on developments in the wider community and topics including wireless, embedded and open source silicon.

IETF Draft Proposes IoT Firmware Update Standard

The Internet Engineering Task Force (IETF) has received a proposal for a cross-vendor standard designed to offer a solid and secure mechanism for updating the firmware of Internet of Things (IoT) devices in the field. Written by Arm engineers Brendan Moran, Milosch Meriac, and Hannes Tschofenig, the draft – titled… Read More

CRU: LMS8001 Companion, Security Alerts, 14nm RISC-V, and More

The LimeSDR open-source software defined radio (SDR) project has received a boost, quite literally, in the form of the frequency-extending LMS8001 Companion Board, announced as part of the LimeSDR Mini crowdfunding campaign. Built around a Lime Microsystems LMS8001 frequency shifter chip, the Companion Board allows any LimeSDR module –… Read More

CRU: Floods, RISC-V for Linux, Iron-Scopes and More

AB Open has announced a partnership with Flood Network to bring a series of Internet of Things (IoT) river level sensors to the Upper Calder Valley, providing valuable flood warning data for the region. Joining the users of the Things Calderdale LoRaWAN network, the flood sensors are to… Read More

CRU: RISC-V Growth, Job Vacancies, and More

Cambridge-based semiconductor specialist UltraSoC has announced its expansion into Bristol, and it’s giving credit for its recent growth to an explosion of interest in the open-source RISC-V instruction set architecture (ISA). “There’s a perfect storm of factors revolutionising the technology business from top to bottom,” says Rupert Baines, UltraSoC’s… Read More

CRU: LoRa Bat Watching, RISC-V Updates, Neural Networks, and More

AB Open’s Andrew Back has written up a project to create a bat detector with LoRaWAN connectivity, transmitting data on bat call measurements via The Things Network using MQTT. “When ODI Leeds recently said that they were interested in LoRaWAN-enabled bat detection, we thought, ‘What a fun idea, let’s… Read More

CRU: LoRaWAN fun, RISC-V education, FPGAs, and more

AB Open’s Andrew Back has written of our work on a LoRaWAN gateway for the region, installed on an iconic 275-feet tall landmark with intermittent power. Part of AB Open’s participation in the IoTUK Boost programme, the installation is designed to provide connectivity to The Things Network’s long-range… Read More

CRU: RISC-V Toolchains, Tiny PCBs, 6502-as-a-Service, and More

Developer Liviu Ionescu has published the results of RISC-V toolchain testing, comparing the GNU MCU Eclipse toolchain to the GCC-based toolchain from SiFive across four configurations. “After releasing GNU MCU Eclipse RISC-V Embedded GCC, I tested if the strategy used while building it is effective,” Liviu explains of his… Read More

CRU: RISC-V Calls for Papers, Industrial Hardware, Equipment Hacking, and More

Calls for papers have gone out for the 7th RISC-V Workshop and the first Workshop on Computer Architecture Research with RISC-V (CARRV), both to be held in the US later this year. The 7th RISC-V Workshop, its organisers have confirmed, is to take place on the 28th to the 30th… Read More

Community Round-Up: RISC-V Progress, Amazon Greengrass, Wuthering Bytes and More

Developer Palmer Dabbelt has submitted a RISC-V port of glibc, the GNU C Library, for upstream inclusion and is actively working with others on a patch set for the Linux kernel with a view to mainline acceptance by Linux 4.14. While the open RISC-V instruction set architecture (ISA) has… Read More

Community Round-Up: RISC-V Workshop Proceedings, Open Virtual Platforms, Cortus’ Core, Arduino Cinque, MinnowBoard Turbot, PIC32MZ with GPU, ARM Cortex-A75, Cortex-A55, Intel Compute Cards, Doubling PWM Resolution, and Gordon Williams on Open Source Challenges

The RISC-V Foundation has publicly published the proceedings of the 6th RISC-V Workshop, held early last month in Shanghai, China. Video and, where appropriate, slide decks have been made available from the three public days of the four-day event. Highlights include updates from Rick O’Connor and Yunsup… Read More

Community Round-Up: RISC-V GCC, Book, Workshop and Licensing, Mentoring GSOC, Linux 4.11 and EdgeX, BrickerBot, and an Open-Source Rigol Firmware

The GNU Compiler Collection (GCC) has hit version 7.1 and now includes support for the RISC-V instruction set architecture (ISA), three decades after the toolkit’s initial 1.0 release. That support for the burgeoning RISC-V open instruction set architecture was coming to GCC was no secret, following the acceptance by the… Read More

Community Round-Up: RISC-V Improvements, Caffe2, PCBA Visualisation, Solar Supercapacitors, Arduino Sigfox, Intel Developer Forums, IoT Requirements Guide, and the Vinduino LoRa Project

Researchers at Princeton University have helped boost the robustness of the burgeoning RISC-V architecture, having developed a tool which has picked up on data storage and retrieval ordering problems that could otherwise have derailed attempts to use it in high-reliability applications. “Incorrect memory access orderings can result in software… Read More