The IoT and sensor network focused Parallel Ultra Low Power (PULP) platform is described as a “silicon-proven parallel platform for ultra-low power computing targeting high energy efficiencies”. It is organised in clusters of RISC-V cores that share tightly coupled data memory and comprised of IPs described in SystemVerilog. The single-core PULPino variant is available now under the permissive Solderpad License, with four different RISC-V core configurations, targeting RTL simulation and synthesis for FPGA, having also been taped-out as an ASIC in UMC 65nm.

In this episode of Open Source Digital Design Insights we got to speak with PULP Project Lead, Davide Rossi, an Assistant Professor at the University of Bologna. Davide provides an introduction to the platform background and architecture, covering in brief some of the academic and industrial collaborators, such as GreenWaves, and in closing looking to the commercial future of the project.