Antmicro has announced the release of Renode 1.7 – quickly followed by version 1.7.1 – with the framework’s first support for time-sensitive networking (TSN) and precision time protocol (PTP) on RISC-V platforms.
An open-source simulation framework popular among those working within the proprietary Arm and open RISC-V ecosystems, and recently praised by Dover Microsystems for helping to significantly shorten the company’s design cycle, the latest release of Antmicro’s Renode brings with it support for new soft-core RISC-V implementations including PicoRV32 and the Murax SoC.
In addition, experimental support for time-sensitive networking (TSN) and precision-time protocol (PTP) has been added to the framework – previously available only as part of the Cadence GEM Ethernet controller, and added as part of Antmicro’s effort to implement TSN and PTP in Zephyr for the Microchip SAM E70.
The new release also brings a range of improvements including better execution determinism, boosted usability, and in the v1.7.1 follow-up release an added integration layer for Verilator which allows for Verilog implementations to be used within a Renode simulation.
More information on the new release is available on the Antmicro blog while the latest version is always available for download on the official Renode website.
Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.