The maintainers of the Wishbone interconnect specification are calling for input on its future evolution, after converting the specification into an editor-friendly format for ease of participation.
Offering eight, 16, 32, and 64 bit widths and originally created by the Silicore Corporation before being released under a permissive licence, the Wishbone bus is a popular choice for cross-core interconnections in free and open source silicon designs. Its maintainers, though, are looking to evolve the standard – and are calling for assistance in doing so.
“Tristan and I have converted the Wishbone spec into a more editor-friendly format (rst). Tristan has thankfully already reviewed the document and you can find the current release candidate for the 3.1 in the GitHub repository,” writes Stefan Wallentowitz on the LibreCores mailing list. “Please suggest changes via PRs in the next three weeks. You can also create a placeholder PR and fill it later to raise a concern or feature. Generic discussion should probably be on this mailing list.”
The call goes out to more than just those looking to revise the specification directly, too. “I would love to have supporting material released along the new spec,” Wallentowitz continues, “like formal models, updated cocotb models, standard bus bridges etc. Contributions are highly welcome!”