Western Digital has announced a strong response to the release of its RISC-V based open silicon SweRV Core, along with the availability of an official implementation for field-programmable gate array (FPGA) use.
Announced back in December 2018 as part of a company-wide initiative to transition data processing products away from proprietary cores to alternatives based on the RISC-V instruction set architecture (ISA), released in January this year, and the subject of a deep-dive analysis by Tom Verbeure last month, Western Digital’s SweRV Core is provided under the Apache Licence 2.0 alongside a simulator dubbed Whisper and a cache coherency fabric.
Now, a few months on from the release, Western Digital has claimed a strong community response. “Western Digital is pleased to provide the SweRV Core to the open source community. The initial response and targeted uses are gratifying to the entire development team and all of Western Digital,” claims Martin Fink, Western Digital chief technology officer. “We look forward to the acceleration of the RISC-V ecosystem and the innovations which will result from this core.”
At the same time, Western Digital is listening to community feedback: the original release has now been joined by an FPGA reference design for use with the Digilent Nexus4 DDR platform, giving those looking to get started a leg-up. This, as with WD’s other releases, is made available under the Apache 2.0 licence.
More details on the latest release can be found on the Western Digital blog.