Western Digital has released a short video discussing how the open RISC-V instruction set architecture is changing its vision for data processing, as it pledges to ship billions of RISC-V cores in its future products.

Western Digital had previously pledged support for the open RISC-V instruction set architecture with the promise that it was to launch data processing products at a rate of a billion RISC-V cores a year – a billion cores which were previously based on proprietary, locked-down instruction set architectures. Now, in a video discussion between vice president of corporate strategy Steffen Hellmold and chief technology officer Martin Fink, the company has revealed more about its vision for the future.

“We already use a lot of compute power to, essentially, control our devices,” Martin explains. “We don’t get too much involved with the data today, as much as we just control the device, and we use a lot of compute capability in order to be able to control the device. So that’s what we’re doing today. As part of this controlling the device, largely what we’ve been doing is storing the information. We haven’t really been doing anything with it, we’ve just really been storing it.

“[RISC-V] is actually a tremendous opportunity for us,” Martin continues, “because this processing power we’ve been using to control the devices is actually decades old, and when we start thinking about applications like machine learning and artificial intelligence, those are new classes of applications and we really, in an ideal world, want to start with a clean sheet of paper. That’s what RISC-V gives us, is the ability to rethink the problem with a clean sheet of paper and not be held back by the rules of the past, by the decades-old stuff. That’s the opportunity with RISC-V, to create new applications that are optimised specifically for the data we’re trying to transform and bring that to our users in a cost-effective and a really effective way.”

More information is available on the Western Digital blog.