Internet of Things (IoT)-focused components provider Seeed Studio has begun stocking the Sipeed Tang Primer FPGA development board, a sub-$18 part which features an Anlogic EG4S20 FPGA running a RISC-V soft core.
Designed to offer a full RISC-V implementation in a very small form factor, the Tang is based around the Anlogic EG4S20 field-programmable gate array (FPGA) with 20,000 logic units, around 130KB of SRAM, and 64Mb of SDRAM on a 32-bit bus. The board also includes 8Mb user-accessible flash memory, an I²C controller for a resistive touch screen, TransFlash card socket, sockets for LCD or VGA video output and DVP camera or high-speed analogue to digital (ADC) input, GPIO breakouts, and a micro-USB socket.
The device comes running the E200 Hummingbird RISC-V soft core, a two-stage ultra-low-power implementation designed to compete with the Arm Cortex-M0+ in embedded applications, in the form of a fork dubbed the E203.
According to Seeed, the board’s target applications include high-speed communication interface interconnection projects, machine vision processing at the edge, parallel computing acceleration, and general education surrounding the RISC-V architecture.
Full details are available on the Seeed Studio store page.
Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.