The open-source QEMU machine emulator and virtualiser has received enhanced support for the open RISC-V instruction set architecture (ISA) in its 4.1.0 release.
Following on from the 4.0.0 release back in April, QEMU 4.1.0 brings a range of improvements to its support for the open RISC-V ISA. Chief among these are the definition of a new “spike” machine, the release of which officially deprecates older machines.
Other improvements include the first support for the RISC-V Privileged Specification 1.11.0, support for SiFive’s general-purpose input/output (GPIO) controller, the ability to make single steps over branches and jumps, correct handling of compressed illegal instructions, bug fixes in the 32-bit syscall application binary interface (ABI), and a cpu-topology device tree node on targets which support such trees.
The latest release also brings with it bug fixes and new features for other architectures, including Arm, MIPS, PowerPC, S390, SPARC, Tricore, x86, and Xtensa, full details of which are available in the changelog.
QEMU 4.1.0 itself can be downloaded from the official website.
Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.