Version 4.0.0 of the QEMU emulator has been released, bringing with it new features for those working with the RISC-V instruction set architecture (ISA).
Designed to allow a system to run code designed for a different instruction set, emulation via QEMU or a similar package is a key part of developing for less-common ISAs like RISC-V – allowing a developer to produce software without requiring access to a hardware implementation, whether that’s a soft core on a field-programmable gate array (FPGA) or a hardware application specific integrated circuit (ASIC).
The open-source QEMU emulator has proven popular among those working with RISC-V, and the new 4.0.0 release brings with it some improvements and enhancements on that front. Chief among these are support for Peripheral Component Interconnect (PCI) and Universal Serial Bus (USB) on the ‘virt board’ virtualised development board, support for symmetric multi-processing (SMP) on the SiFive_u virtual machine, and support for transmission interrupts on the SiFive UART.
Other RISC-V improvements include additional fields in mstatus, three states – dirty, clean, and off – for the FS field, support for writing to the misa CSR, and support in the in-built gdbserver for register lists as XML files. These are in addition to a range of improvements and enhancements for other ISAs supported within QEMU.
More information on the new release is available on the QEMU wiki.
Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.