The Parallel Ultra-Low Power (PULP) Platform project has announced tape-out of Urania, an implementation of its bigPULP design which combines one Ariane core with two quad-core RISC-V clusters.

Announced back in February last year, Ariane is a 64-bit application-class RISC-V core design, created as a joint effort between ETH Zurich and the University of Bologna. RI5CY, meanwhile, is a 32-bit RISC-V core design popularised by the PULPissimo microcontroller platform. Now, the pair have been combined in a single system-on-chip (SoC) dubbed Urania, for the Urania Sternwarte observatory in Zurich – itself named for the Greek muse of astronomy.

“We have recently taped out a couple of chips. One of them is Urania, [a] BigPULP implementation with one Ariane core and two clusters each with 4x RI5CY cores and a DDR interface,” the PULP Platform team announced via Twitter this week. “Urania is a big leap forward,” adds PULP’s Luca Benini. “We never tried so many new things in a single SoC. Exciting ride: thanks to Andreas, Beat and the team for the heroic effort!”

Designed on a 64nm process node, targeting a 100MHz clock and packaged as QFN64, the Urania SoC marks the first application-specific integrated circuit (ASIC) implementation of the bigPULP architecture, first unveiled as part of the HERO Heterogeneous Research Platform. In its initial design, the chip includes a single 64-bit Ariane core and two clusters of four 32-bit RI5CY cores with floating-point units (FPUs), alongside the PULPo first-order optimisation hardware acceleration unit and a DDR3 memory interface.

More details on Urania can be found on the project website.