The Parallel Ultra-Low Power (PULP) Platform has announced that Silicon Labs has adopted the platform to extend and customise embedded processor cores in their integrated circuit designs.
Now approaching its sixth year, having been launched by Luca Benini at the University of Bologna back in May 2013, the PULP Platform’s numerous projects include the Hero open heterogeneous research platform, the RISC-V Ariane core and extended OpenPiton+Ariane design in partnership with the OpenPiton project, and its cores can be found in devices from companies including OpenISA and GreenWaves Technologies.
The project’s latest partnership win has just been announced: a partnership with Silicon Labs. “They work with us to extend and customise the functionality of processor cores for deeply embedded heterogeneous apps for their IC products,” the PULP Platform explains “They also have a uC/OS version for RISC-V and planned a port to PULP.”
Silicon Labs has made no official announcement detailing the partnership, but did provide information on its efforts with the RISC-V open instruction set architecture (ISA) in a presentation at the RISC-V summit in December last year (PDF warning).
Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.