Olof Kindgren, director of the Free and Open Source Silicon Foundation (FOSSi Foundation), has released a tool designed to make multi-sensor aggregation on field-programmable gate arrays (FPGAs) simpler: the RISC-V-powered Observer.

“Implementing the logic for sensor communication, post processing and format conversion directly in an FPGA can quickly become very time-consuming. This is a task much better suited for a CPU,” Kindgren explains of the project. “On an FPGA it’s no problem to add a soft CPU, but the more sensors that are connected to the CPU, the harder it will have to keep up with any real-time aspects of the data collection.

“Observer deals with this by attaching a CPU to each sensor interface that handles all bring-up and data collection from the sensor and produces a well-formed data packet which is then forwarded to a common aggregation node.”

The Observer platform is built on free and open-source silicon: a Collector, which interfaces directly with each sensor over whatever protocol is required, connects to a Base via the open Wishbone interconnect standard; each Base includes a compact SERV RISC-V CPU core given the task of controlling data flow and sending the data to a shared Emitter via an AXI stream; the Emitter contains another SERV core and aggregates all incoming data for transmission over a UART serial bus.

“This has a number of benefits,” Kindgren explains of the approach. “Data collection and post-processing from each sensor can be done completely independent of the others. It allows for power savings by doing complex data reduction very close to the sensor and allowing unused nodes to shut down when not in use. Depending on the complexity of the sensor interfacing or post processing, each node can independently decide to do this using a couple of lines of assembly code, a bare-metal C program or even run a RTOS such as Zephyr.”

Observer is available now on Kidngren’s GitHub repository.