An initial programme for ORConf 2018, the open-source digital design conference to be held in Gdansk, Poland this September, has been published – and there are some big names showing off the state of the art on the schedule.
While there are more speakers yet to be announced, the initial schedule for ORConf 2018 is already shaping up to be the most impressive list of heavy-hitters yet – including Wilson Snyder, who will be presenting on the Verilator 4.0 multi-threaded Verilog simulator he co-authors. Tim ‘mithro’ Ansell, meanwhile, has been confirmed as presenting SymbiFlow, a project which aims to be the equivalent to the GNU Compiler Collection (GCC) for field-programmable gate arrays (FPGAs).
Other confirmed speakers include: Julius Baxter on Morse Micro’s adaptation of the Rocket RISC-V core generator for single-chip 802.11ah use; Charles Papon, creator of the Scala-based SpinalHDL hardware description language project; Ben Reynwar on Python as a language for testing and code generation as found in FuseSoC and its generators; Germán Cano Quiveu on booting OpenRISC system-on-chips via a Wi-Fi-enabled open bootloader; Philipp Wagner on the Open SoC Debug (OSD) specification and the LibreCores project; and Dan Gisselquist on the lessons learned while formally verifying the ZipCPU design.
Hosted by the Gdansk University of Technology, ORConf 2018 takes place between from the 21st to the 23rd of September. More information is available on the official website.
Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.