Google Research has released the source code for a chip floor-plan generate based on deep reinforcement learning – after publishing a paper demonstrating how effective the approach could be in April last year.
“Chip floorplanning is the engineering task of designing the physical layout of a computer chip,” the research team explained in the abstract to their paper. “Despite five decades of research, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts.
“Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area.”
The secret: turning reinforcement learning on the task, creating an edge-based graph convolutional neural network (CNN) which is capable of learning – becoming better and faster at the problem as it tackles more chips.
Now, the technology behind the paper has been released under a permissive licence for all to use.
“Our hope is that Circuit Training will foster further collaborations between academia and industry, and enable advances in deep reinforcement learning for Electronic Design Automation, as well as, general combinatorial and decision making optimisation problems,” the team writes of the release.
“Capable of optimising chip blocks with hundreds of macros, Circuit Training automatically generates floor plans in hours, whereas baseline methods often require human experts in the loop and can take months.”
“ML [Machine Learning] and automation can make chip design much faster and cheaper in the next few years,” predicts Azalia Mirhoseini, staff research scientist at Google Brain and first author of the original paper, “and as a result we’ll have many more performant specialised chips.”
The original paper, published in the journal Nature, is available to read online; the Circuit Training source code, with examples including a RISC-V chip, has been published to GitHub under the permissive Apache 2.0 licence.