A call-to-arms has been raised by the Embench team for assistance in developing a new, fully-open benchmark suite designed to offer embedded developers an alternative to the products of the Embedded Microprocessor Benchmark Consortium (EMBC).
As detailed in an article on EE Times, the Embench team is working to produce an open-source benchmark for embedded developers which distils performance metrics from around 20 real-world applications into a single score. This score will be relative to a baseline implementation, which is currently based on the PULP Platform’s RI5CY 32-bit RISC-V core.
Launched in January by RISC-V pioneer David Patterson and boasting the support of other luminaries including SiFive’s Palmer Dabbelt and Embecosm’s Jeremy Bennet, the team behind the benchmark effort is to present its progress at the RISC-V Zurich workshop this week – and is calling for volunteers to assist with the effort.
“Dhrystone and Coremark have been the de facto standard microcontroller benchmark suites for the last thirty years, but these benchmarks no longer reflect the needs of modern embedded systems,” the team explains. “Embench was explicitly designed to meet the requirements of modern connected embedded systems. The benchmarks are relevant, portable, and well implemented.”
More information is available on the official website.
Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.