The Internet Engineering Task Force (IETF) has received a proposal for a cross-vendor standard designed to offer a solid and secure mechanism for updating the firmware of Internet of Things (IoT) devices in the field.

Written by Arm engineers Brendan Moran, Milosch Meriac, and Hannes Tschofenig, the draft – titled “A Firmware Update Architecture for Internet of Things Devices – proposes an architecture which allows firmware images to be safely and secure transferred across any available transport mechanism.

“Vulnerabilities with IoT devices have raised the need for a solid and secure firmware update mechanism that is also suitable for constrained devices,” the draft’s abstract reads. “Incorporating such update mechanism to fix vulnerabilities, to update configuration settings as well as adding new functionality is recommended by security experts. This document specifies requires and an architecture for a firmware update mechanism aimed for Internet of Things (IoT) devices. The architecture is agnostic to the transport of the firmware images and associated meta-data.”

The draft, which expires in May 2018, can be read in full on the IETF website.

The LoRa Alliance, responsible for the LoRaWAN long-range low-power wireless network standard, has announced the release of a new revision which brings with it support for global roaming.

Announced during the All Members meeting in China, the LoRaWAN 1.1 standard brings support for global handover roaming, Class B, and security enhancements, while the new LoRaWAN Backend Interfaces 1.0 standard introduces the ability to decompose the network into interoperable nodes – designed, its creators explain, to provide full support for roaming between networks from differing vendors. A final additional specification, LoRaWAN 1.1 Regional Parameters Revision A, describes region-specific radio parameters to which end devices should adhere.

“For the IoT to reach its forecast potential, an ability to deploy devices on a massive scale is a key enabler,” explains Geoff Mulligan, chair of the LoRa Alliance, of his organisation’s latest standards. “The enhancements introduced today advance the LoRaWAN protocol, further opening up the ecosystem, enhancing interoperability and expanding the reach of existing LoRaWAN networks.”

The latest standards are available upon request to the LoRaWAN Alliance via the official website, while The Things Network has produced an informational video.

Broadcom has issued an offer to buy rival chip maker Qualcomm in a deal valued at nearly £100 billion – to include NXP Semiconductor, should Qualcomm’s own acquisition go through – further shrinking the embedded and communications chip markets.

Following ongoing legal battles with Apple, Qualcomm’s largest customer, and reports that the company is to move to Intel for its modem chips, Broadcom has offered £98.8 billion to acquire Qualcomm – a deal which is to include NXP providing Qualcomm’s own offer to buy that company goes through successfully. If successful, the offer would create a company with a combined $51 billion plus revenue.

“We have great respect for the company founded 32 years ago by Irwin Jacobs, Andrew Viterbi and their colleagues, and the revolutionary technologies they developed,” claims Broadcom chief executive and president Hock Tan. “Following the combination, Qualcomm will be best positioned to build on its legacy of innovation and invention. Given the common strengths of our businesses and our shared heritage of, and continued focus on, technology innovation, we are confident we can quickly realize the benefits of this compelling transaction for all stakeholders. Importantly, we believe that Qualcomm and Broadcom employees will benefit from substantial opportunities for growth and development as part of a larger company.”

The offer has, however, been soundly rejected by Qualcomm, which has claimed it significantly undervalues the company – despite representing a premium on its current stock value. At the time of writing Broadcom had not come back with a counter offer.

The creators of the Shakti Processor Project, which aims to build a RISC-V design capable of scaling from embedded to high-performance compute (HPC) tasks, have announced they are to begin chip manufacture in the first half of 2018.

During a detailed interview with Factor Daily held at the Indian Institute of Technology, Madras, Professor V. Kamakoti and project advisor G.S. Madhusudan revealed that the five-year-and-counting project is heading to manufacturing next year in the form of the C-Class microcontroller variant. Once proven, this will be joined at future dates by I-Class, M-Class, S-Class, and H-class microprocessor implementations, each offering improved performance and capabilities, along with an experimental variant dubbed the T-Class which is designed for use in security-critical projects.

More information on the Shakti Processor Project can be found in an Open Source Digital Design Insights (OSDDI) video which was filmed under difficult conditions in October 2015 and in which research students Rahul Bodduna and Arjun Menon offer an overview of the project.

AB Open’s own Andrew Back has spent some time with the Microchip SODAQ Explorer, a LoRaWAN development platform designed to be as easy to use as an Arduino yet with fully wireless operation capabilities.

“The Explorer is a well thought out little board that should be well suited to workshops — in particular where not everyone has real programming experience — enabling participants to get up and running quickly with putting LoRaWAN and simple applications to the test,” Andrew concluded. “Although there is only a temperature sensor on-board, others could be connected up with ease and the Arduino ecosystem provides support for many different types.”

Andrew’s full hands-on review can be found elsewhere on the site.

Linus Torvalds officially released Linux 4.14 this weekend, a six-year long-term support (LTS) version of the kernel with a wide range of improvements.

“No surprises this week,” says Linus of the release, “although it is probably worth pointing out how the 0day robot has been getting even better,” referring to the kernel’s new ability to detect and withstand so-called ‘zero-day’ security vulnerabilities. “It was very useful before, but Fengguang [Wu] has been working on making it even better and reporting the problems it has found.”

Headline changes in the new kernel include support for 128 petabytes (PiB) of virtual and 128 PiB of physical memory address space, support for AMD’s new Secure Memory Encryption functionality, a new ‘zstd’ compression algorithm for Brtrfs and SquashFS file systems, and a zero-copy mechanism from user memory to sockets, along with an extension to the LTS schedule that will see the kernel supported for a full six years.

CNXSoft has further gathered together the improvements of interest to embedded developers working on the ARM and MIPS instruction set architectures.

For many, though, it will be Linux 4.15 that brings the most excitement, thanks to the merging of contributions for OpenRISC symmetric multiprocessing (SMP) and the first upstream RISC-V port.

Support for symmetric multiprocessing on the OpenRISC platform comes courtesy of developer Stafford Horne, based on patches originally written in 2014. Visible in a merge commit message, the pull by Linux creator Linus Torvalds adds support for running multiple OpenRISC cores in a single Linux system. “It took time to get it just right,” says Michael of the pull, following his announcement on Twitter of Linus’ acceptance.

Linus has also formally merged support for a RISC-V port of the Linux kernel, announcing the move via the Linux Kernel Mailing List. While the port had been sent upstream previously, it required additional work before finally being accepted into the Linux 4.15 tree – meaning that the next release of the kernel will be the first to boast mainstream RISC-V support alongside its OpenRISC SMP support.

Open silicon specialist SiFive has announced another win for its DesignShare platform with Analog Bits, provider of low-power mixed signal intellectual property, adding its precision clocking macros into the mix.

Designed to make it simpler for start-ups to build custom silicon by bringing together as much of the IP required to design a system-on-chip (SoC) as possible, DesignShare has enjoyed some high-profile success of late. Earlier this month Flex Logix announced it was adding its embedded field-programmable gate array (eFPGA) technology to the platform, while back in August Rambus did the same with its security tech – and now Analog Bits has joined the fold.

“For two decades Analog Bits has been an important supplier of low-power IP for use in SoC devices and helped spawn the mobile and computing revolution,” says Mahesh Tirupattur, executive vice president, of the company. “Through DesignShare, we hope to empower more system developers and provide them with the competitive edge they need to deliver innovative SoC products in a timely manner.”

“The addition of Analog Bits to the DesignShare ecosystem provides engineers with a faster and more efficient way to bring SoCs to market,” adds Shafy Eltoukhy, SiFive’s lead on the DesignShare programme. “The adoption of the RISC-V architecture continues to experience significant growth, and with Analog Bits as part of the DesignShare movement it will be easier and more flexible for designers to employ RISC-V in their future designs across a wide range of implementations.”

Finally, the Open Source Hardware User Group and BCS Open Source Specialist User Group have announced an evening of RISC-V themed talks on Thursday 23rd November.

Playfully entitled, “RISC-V, RISC-V, RISC-V“, the joint meeting of OSHUG and BCS OSSG will play host to talks on Bringing up cycle-accurate models of RISC-V cores and FreeBSD/RISC-V and Device Drivers, with a third talk to be confirmed. The first will be given by Edward Jones of Embecosm, who will a present a report of their experience bringing up cycle-accurate models of two cores in particular, RI5CY from the PuLP project, and Clifford Wolf’s PicoRV32.

The second talk, from Ruslan Bukin, a Research Associate at University of Cambridge Computer Laboratory, will describe the current status of FreeBSD/RISC-V, toolchain and supported simulators. Ruslan will also cover the porting process, in addition to describing the latest changes made to FreeBSD in order to support the latest RISC-V privilege specification (v1.10).