Huami, a subsidiary of Chinese electronics specialist Xiaomi, has announced a new family of smartwatches and fitness wearables, and in doing so is set to become the first company to bring a product based on the open RISC-V instruction set architecture (ISA) to the consumer market.

Announced by Huami at its technology event in Beijing this week, the Huangshan No. 1 system-on-chip (SoC) is based on the SiFive E31 processor core intellectual property (IP), which is itself based on the open RISC-V instruction set architecture (ISA). To launch in Amazfit-branded smartwatch and fitness band wearable devices, the Huangshan No. 1 features the SiFive E31 as its main processor, operating alongside an always-on (AON) module designed to transfer sensor data to internal static RAM without waking the primary processor, plus dedicated accelerators for neural network workloads.

During the event, Huami described RISC-V – which began life just eight years ago at the University of California, Berkeley, and which requires no expensive licensing in order to develop open- or closed-hardware implementations – as “the processor architecture of the era,” stating that it is “very suitable for small embedded systems and the Internet of Things (IoT).”

“This is a milestone,” SiFive chief architect and RISC-V Foundaiton chair Krste Asanovic says of the new processor. “The cooperation between Huami Technology and SiFive brings RISC-V technology to humans, on their wrist.”

Huami may be the first to market with a RISC-V consumer product, but it’s not likely to be alone for long: SiFive chief executive and president Naveed Sherwani has stated that “more innovative products featuring SiFive technology” will be announced soon, though has not yet provided details.

More information is available in Huami’s product announcement.

For those already experimenting with RISC-V via the SiFive HiFive Unleashed development board, Ground Electronics – AB Open’s manufacturing division – has launched a custom-designed case with room for cooling.

“It’s no secret that we’re huge fans of the RISC-V free and open instruction set architecture (ISA),” explains Andrew Back, “and when the HiFive Unleashed board was announced, we didn’t hang about and backed the campaign in an instant. Of course, it wouldn’t do to have the board just sitting on the workbench without any form of protection, so we put together a simple case cut from Midnight Black Perspex for the base and Clear Perspex for the top.”

The cases, which include a cut-out to provide the heatsink and fan assembly with access to cool air, are available now from the Ground Electronics store priced at £20 (exc. VAT).

The Parallel Ultra-Low Power (PULP) Platform team has announced the release of its latest creation: HERO, the open heterogeneous research platform combining an FPGA-based RISC-V many-core accelerator with an Arm Cortex-A host processor.

“HERO combines a PULP-based open-source parallel many-core accelerator implemented on FPGA with a hard ARM Cortex-A multicore host processor running full-stack Linux,” its creators explain. “HERO is the first heterogeneous system architecture that mixes a powerful ARM multicore host with a highly parallel and scalable many-core accelerator based on RISC-V cores.

“HERO offers a complete hardware and software platform which advances the state of the art of transparent accelerator programming using the OpenMP v4.5 Accelerator Model. The programmer writes a single application source file for the host and uses OpenMP directives for parallelisation and accelerator offloading. Lower-level details such as differing ISAs as well as shared virtual memory (SVM) between host and accelerator are handled by our heterogeneous toolchain based on GCC 7, runtime libraries, kernel driver and our open-source hardware IPs.”

The platform itself, created in partnership with the Eurolab-4-HPC2 project, is based on a Xilinx Zync ZX706 evaluation kit running an eight-core 32-bit RI5CY-based “Mr. Wolf” PULP cluster with 256KiB of shared L1 scratchpad memory, 4KiB of shared L1 instruction cache, 256KiB of shared L2 scratchpad and instruction memory, and a newly-developed input–output memory management unit (IOMMU) featuring 32 variable-size entry L1 and 1,024 page-size entry transaction lookaside buffers (TLBs).

More information on Hero, which is released under the Apache Licence 2.0, can be found on the official website.

Western Digital, meanwhile, has released a short video discussing how the open RISC-V instruction set architecture is changing its vision for data processing, as it pledges to ship billions of RISC-V cores in its future products.

Western Digital had previously pledged support for the open RISC-V instruction set architecture with the promise that it was to launch data processing products at a rate of a billion RISC-V cores a year – a billion cores which were previously based on proprietary, locked-down instruction set architectures. Now, in a video discussion between vice president of corporate strategy Steffen Hellmold and chief technology officer Martin Fink, the company has revealed more about its vision for the future.

“We already use a lot of compute power to, essentially, control our devices,” Martin explains. “We don’t get too much involved with the data today, as much as we just control the device, and we use a lot of compute capability in order to be able to control the device. So that’s what we’re doing today. As part of this controlling the device, largely what we’ve been doing is storing the information. We haven’t really been doing anything with it, we’ve just really been storing it.

“[RISC-V] is actually a tremendous opportunity for us,” Martin continues, “because this processing power we’ve been using to control the devices is actually decades old, and when we start thinking about applications like machine learning and artificial intelligence, those are new classes of applications and we really, in an ideal world, want to start with a clean sheet of paper. That’s what RISC-V gives us, is the ability to rethink the problem with a clean sheet of paper and not be held back by the rules of the past, by the decades-old stuff. That’s the opportunity with RISC-V, to create new applications that are optimised specifically for the data we’re trying to transform and bring that to our users in a cost-effective and a really effective way.”

More information is available on the Western Digital blog.

OpenMV, an open-source machine vision start-up founded by Kwabena W. Agyeman and Ibrahim Abdalkader, has launched a crowdfunding campaign for its latest creation: an open camera module based on the popular MicroPython environment.

“The OpenMV project is about creating low-cost, extensible, Python powered, machine vision modules and aims at becoming the ‘Arduino of Machine Vision,’” the pair explain of the company’s founding precepts. “Our goal is to bring machine vision algorithms closer to makers and hobbyists. We’ve done the difficult and time-consuming algorithm work for you leaving more time for your creativity!

“The OpenMV Cam is like a super powerful Arduino with a camera on board that you program in Python. We make it easy to run machine visions algorithms on what the OpenMV Cam sees so you can track colours, detect faces, and more in seconds and then control I/O pins in the real-world. The OpenMV Cam H7 is the next generation OpenMV Cam model following the successful OpenMV Cam M7 which has sold more than 10K units to date.”

As well as visible-light vision, the OpenMV Cam H7 includes support for FLIR’s Lepton family of thermal imaging modules, support for global rather than rolling shutter captures, and the ability to run simple convolutional neural networks (CNNs) directly on the Arm Cortex-M7-based device or to farm off heavier processing to an external system such as a Raspberry Pi.

The campaign is live now on Kickstarter with a $50,000 goal; the basic OpenMV Cam H7 with pre-focused OV7725 camera module starts at $49 (around £37 excluding taxes). More information is available on the campaign page.

OsmocomBB SDR PHY, a project to replace the currently-proprietary Layer 1 of the Osmocom GSM mobile baseband stack, has announced a major milestone: unlocking the ability to run a cellular network on any radio frequency, including unlicensed frequencies.

The Osmocom project was founded with a laudable goal: to create a stable software stack with supporting tools for a variety of mobile communications standards, all of which is based on open source technologies. In the years since its launch, the project has enjoyed considerable success – but the physical layer of its mobile baseband subproject OsmocomBB has been locked away behind proprietary technology. Enter OsmocomBB SDR PHY: an effort to replace proprietary Layer 1 PHY with software-defined radio devices.

“A few weeks ago, the first milestone has been completed – ‘Ability to run GSM network on any frequency,’” writes Osmocom’s Vadim Yanitskiy. “We have managed to run a GSM network in 2.4 GHz Wi-Fi band, connect an SDR-based phone and successfully tested the regular subscriber’s activity, such as SMS messaging and voice calls. More details about this feature will be shared soon.”

Besides opening up the telecommunications stack still further, the OsmocomBB SDR PHY project’s milestone achievement means that it will theoretically be possible for enthusiasts and hobbyists to run small-scale low-power GSM networks on unlicensed spectrum in the Industrial, Scientific, and Medical (ISM) bands without the need to apply for a formal licence – a move which opens the technology up to a considerably wider audience than ever before.

More information is available from Vadim’s announcement and the freshly-created OsmocomBB SDR PHY wiki page.

Computing giant Intel has announced its continued support in favour of open firmwares, having recently announced the release of Intel Slim Bootloader for Internet of Things (IoT) devices ahead of the first Open Source Firmware Conference (OSFC) this week.

“The adoption of open source has had a significant impact on software development over the past few decades,” explains Intel’s Michael Greene. “As those principles influence overall platform design, Intel continues to expand the use of open source in platform firmware development. Events like the Open Source Firmware Conference (OSFC) allow Intel to engage with the community on a broad set of platform solutions.

“While most off-the-shelf platforms ship [with] UEFI [Unified Extensible Firmware Interface] to maximise compatibility, specialised platforms may launch their software payload with coreboot, LinuxBoot, or a custom bootloader for tighter integration. No matter the solution, Intel customers expect their silicon to be properly initialised and behave consistently across solutions. To provide this consistency, developers can integrate Intel Firmware Support Package (Intel FSP) into their bootloader to initialise Intel silicon. This royalty-free solution handles the processor, memory controller, and Intel chipset initialization functions not currently available in open source. Intel FSP uses a simplified licensing agreement, allowing redistribution as part of an open source project or commercial solution.

“Intel FSP is a key component of Intel Slim Bootloader,” Michael continues, “a new scalable firmware solution for Internet of Things (IoT) devices. Slim Bootloader, which brings simplicity, is ideal for integrated industrial IoT solutions and real-time operating systems (RTOS) with minimal firmware requirements.”

Intel will be presenting its open firmware efforts, including the Slim Bootloader, at the Open Source Firmware Conference today through to the 15th of September. More information is available on the event website, while Michael’s full post can be found on the Intel website.

Finally, the world’s first Festival of Maintenance is scheduled to take place this weekend in London, offering attendees a look at the sustainability of making and the importance of maintenance – something all-too easily overlooked in the race towards innovation.

The Internet of Things (IoT) is a classic example of an innovation-driven industry: developers and manufacturers receive far more praise and focus for working on something new and shiny than for improving or maintaining something which already exists. Maintenance, though, is critical: while alleged cases of built-in obsolescence may fly in the world of smartphones and games consoles, IoT devices should be expected to perform for years or even decades at a time.

As a way of bringing light to the issue of maintenance, a group of makers and engineers are launching the Festival of Maintenance in London later this month. “We were inspired by discussions at Maker Assembly,” the team behind the event explain, “where we discussed the sustainability of making, maker communities and maker spaces, and the way that innovation and new things are championed, whereas maintenance is often less visible, less valued – and yet essential.”

The event is scheduled for the 22nd of September 2018 at the University of London Union’s Conferences Central venue. Confirmed speakers include Natalie Kane of the V&A Museum, Alanna Irving of the Open Collective, Doteveryone’s Alex Mecklenburg, DoES Liverpool’s Adrian McEwen, and Chris Hellawell of the Edinburgh Tool Library, speaking in five sessions on topics from new models for maintenance to communities and voluntary maintenance.

More information is available, along with tickets, from the official website.