Calls for papers have gone out for the 7th RISC-V Workshop and the first Workshop on Computer Architecture Research with RISC-V (CARRV), both to be held in the US later this year.

The 7th RISC-V Workshop, its organisers have confirmed, is to take place on the 28th to the 30th of November 2017 and will be hosted by Western Digital in Milpitas, California. Those interested in presenting are asked to pick one of the two possible talk lengths – 25 minutes or 12 minutes – and to participate in the poster session for extended discussions. Submissions are to be in PDF format of no more than two pages, and should be submitted through the official website no later than the 17th of September.

The Workshop on Computer Architecture Research with RISC-V, meanwhile, is to have its inauguration alongside the IEEE Micro conference on the 14th of October 2017 in Boston, Massachusetts. The workshop, its organisers explain, is “intended to be highly interactive with an open session discussing experiences with using the current state of the RISC-V ecosystem for architecture research and what directions to take to improve it.” Suggested topics include RISC-V simulation and emulation infrastructures, RISC-V RTL cores, whole-SoC simulators and emulators, research prototypes, formal models, compiler toolchains, security architecture and memory model research, and quantitative comparisons of RISC-V with other instruction set architectures such as MIPS and ARM. Submissions for CARRV should be made via the official website before the 1st of August.

Analytics specialist UltraSOC has announced the first processor trace implementation for RISC-V, based on a specification it is to offer to the RISC-V Foundation to form part of the standard and to assist developers with analysis and diagnosis.

“RISC-V is a great architecture: but an architecture is not enough,” explained Rupert Baines, UltraSoC chief executive, of his company’s creation. “Customers need the whole ecosystem – an ecosystem that puts designers in control and empowers innovation. UltraSoC is aiming to play a major role in that with our debugging and development IP, and processor trace for RISC-V is a significant supporting pillar in that effort.”

The company has confirmed it is working with all the major RISC-V core vendors, including Andes, Codasip, Roa Logic, SiFive, and Syntacore, but warns that public availability of the processor trace isn’t due until the fourth quarter of this year. The processor trace format, meanwhile, is to be offered to the RISC-V Foundation for inclusion in the official open-source standard itself.

Lattice Semiconductor has announced the launch of new field programmable gate array (FPGA) reference designs featuring Long-range Radio (LoRa) communications and machine learning capabilities: the iC40 UltraPlus.

“The new iCE40 UltraPlus solutions underscore our commitment to continuously provide our customers with updated resources for designing solutions for new markets quickly,” claimed C.H. Chee, senior director of marketing at Lattice, of the launch. “With improved DSP performance, flexible I/Os and increased memory for buffering, the iCE40 UltraPlus brings added intelligence to smartphones and IoT Edge products, and security to the Cloud.”

The iCE40 UltraPlus features eight times more memory than the original iCE40 Ultra at 1.1Mbit, twice the digital signal processors (DSPs) at a total of eight, and improve input-output (IO) capabilities. Reference designs provided for implementation on the iCE40 UltraPlus include machine learning and on-device artificial intelligence for low-power human face detection, control of a LoRa-compatible radio module, ultra-low-power graphics acceleration, and on-device encryption of sensor data prior to transmission.

More information on the Lattive iCE40 UltraPlus is available from the official website.

Canonical has announced that Ubuntu Core, its Linux distribution tailored specifically for embedded platforms, is now available for the Raspberry Pi Compute Module 3 (CM3) computer-on-module (COM).

“Raspberry Pi has long been considered the compute board of choice for developers and innovators,” claimed Canonical executive vice president Mike Bell at the launch, “and the CM3 with Ubuntu Core creates a fantastic way to successfully deploy devices in production.” Raspberry Pi (Trading)’s chief executive Eben Upton, co-inventor of the original Raspberry Pi single-board comptuer (SBC) added: “Gaining official support for Ubuntu Core is highly significant for our Compute Module 3. It opens up a huge community of developers keen to leverage Ubuntu’s particular advantages in the IoT world; its resource-efficient footprint, versatility, and industry leading security benefits.”

Ubuntu Core is a central pillar of Canonical’s stated vision for embedded computing, as is its ‘Snappy’ packaging system which bundles software up for ease of installation, maintenance, and which offers the ability to quickly roll-back changes without modifying other software on the system.

For those looking to implement the Raspberry Pi Compute Module 3 in an industrial environment, Kunbus has announced the RevPi Core 3 as a follow-up to its earlier RevPi Core.

Designed for tasks more demanding than the original single-core RevPi Core could support, the RevPi Core 3 benefits from the Raspberry Pi CM3’s quad-core BCM2837 processor, 1GB of RAM, and 4GB of embedded storage. As with its predecessor, Kunbus provides the RevPi Core 3 with a pre-installed Raspbian Jessie Linux patched for real-time operation and in a housing meeting the EN61131-2 standard for industrial use.

According to Kunbus, the RevPi Core 3 supports power supplies from 10.7V up to 28.8V, can operate in temperatures between -40 to 55°C, is protected against electrostatic discharge and other surge sources up to 8kV. Full details are available from the official website.

MediaTek has announced the launch of a new system-on-chip (SoC) targeting narrowband Internet of Things (NB-IoT) projects using the 3GPP Low-Power Wide-Area (LPWA) technology suite for wireless connectivity.

“LPWA has the power to truly unleash the potential of the IoT, representing a huge market opportunity,” claimed MediaTek’s Jerry Yu at the launch of the MT2625 SoC, which at 16mm x 18mm is claimed to be the world’s smallest. “MediaTek was the first in the industry to support the full frequency band of 3GPP NB-IoT standards, and we are committed to continuing to invest in NB-IoT technology to meet the global market demand. By providing highly integrated, low power and robust connectivity technologies over the years, along with full-featured IoT software and hardware development platforms, MediaTek aims to enable developers and device makers of all sizes to quickly bring to market innovative NB-IoT devices.”

The MT2625 includes an ARM Cortex-M microcontroller running at 104MHz, 4MB of pseudo-static RAM (PSRAM), 4MB of NOR flash memory, and integrated power management unit (PMU), baseband processor, radiofrequency module and model digital signal processor (DSP) for connectivity to any band defined in the 3GPP Release 14. More details are available on the official product page.

For those working on lower-frequency Low-Power Wireless Area Network (LPWAN) implementations, Antenova has announced a surface-mount antenna measuring just 12mm x 11mm and 1.6mm in thickness.

Designed for use with the 863-870MHz and 902-928MHz spectrum bands, Antenova’s Grandis antenna promises compatibility with LPWAN standards including LoRa, SigFox, and Wightless-P along with any other protocols using those frequencies. “The market for LPWAN connections is expanding and we are aware of a large number of customer applications that need a small antenna with strong performance,” said Antenova chief executive Colin Newman of his company’s launch. “This antenna meets those requirements very well.”

The Grandis is joined by a 2.4GHz antenna, Zenon, for use with Bluetooth, Wi-Fi, and ZigBee connectivity. According to Antenova, the Zenon antenna – the first in its new family of Reflector antennas – measures a mere 23mm x 16mm and is, like the Grandis, just 1.6mm thick and supports mounting directly onto metal surfaces. More information on both antennas can be found on the Antenova website.

Husarion has officially hit crowdfunding site Crowd Supply with its second microcontroller-based prototyping platform for robotics projects: the Core2.

Available in two variants – the standard CORE2 plus the CORE2-ROS, the latter featuring a Raspberry Pi 3 or Asus Tinker Board single-board computer (SBC) and the Robot Operating System (ROS) – the CORE2 boards include built-in DC motor ports for four motors with hardware processing of quadrature encoder inputs, six servos with an on-board DC/DC converter configurable on a per-port basis, and an impressive array of general-purpose input-output (GPIO) connectivity. The board itself is powered by an ARM Cortex-M4 microcontroller running at 168MHz with 192KB of RAM and 1MB of flash memory.

Full details of the Husarion Core2 and its ROS-powered variant can be found on the project’s Crowd Supply campaign page, while the software framework is available on GitHub under the MIT Licence.

Elliot Williams has written of his experiments in improving an off-the-shelf inspection microscope on Hackaday, adding Wi-Fi connectivity and scriptable remote control to an ultra-low-cost device from a Chinese supplier.

“I sent just over $40 off to my close friend Alibaba, and a few weeks later was the proud owner of a halfway usable inspection scope that records stills or video to an SD card,” Elliot writes. “Unfortunately, it’s only halfway usable because of chintzy interface design and a wobbly mount. So I spent an afternoon, took the microscope apart, and got it under microcontroller control, complete with Wi-Fi and a scripting language. Much better! Now I can make microscope time-lapses, but much more importantly I can take blur-free photos without touching the wiggly rig.”

Full details of the modifications, which use the STM32F103 microcontroller development board, are available on Hackaday, while the FORTH code used to control the inspection scope is available on GitHub.

Finally, Roberto Barrios has written up his own experiments in modifying an oscilloscope to make it more accessible to those suffering from deuteranopic (red-green) colourblindness.

Roberto’s modification involved getting inside his Agilent DSO-X 3032A and rewiring the LCD to swap the red and blue signals – not an easy task given the small size of the connectors. “The problem is the 0.5mm pitch of the connector and that I wanted to test this quickly, I did not want to design PCB and wait a few weeks to receive it. That meant using 0.1mm wires to route each signal individually from one connector to the other and using Kapton tape to insulate the three ‘layers.’ An hour under the microscope and it was done.”

The results are impressive: instead of shades of yellow and green which are to many suffering from colourblindness entirely indistinguishable, the modified DSO-X displays the first channel trace in a shade of blue – immediately and obviously distinct from the still-green second channel. It’s an impressive hack, but one which Roberto himself laments had to be done: “Back in time, HP was a lot more careful about these things. Take the old 70004 MMS display, for example: It not only allows you to change colours, it even has two colourblind palettes built-in. The manual has a full chapter on colour theory and colour options.”