An initial programme for ORConf 2018, the open-source digital design conference to be held in Gdansk, Poland this September, has been published – and there are some big names showing off the state of the art on the schedule.

While there are more speakers yet to be announced, the initial schedule for ORConf 2018 is already shaping up to be the most impressive list of heavy-hitters yet – including Wilson Snyder, who will be presenting on the Verilator 4.0 multi-threaded Verilog simulator he co-authors. Tim ‘mithro’ Ansell, meanwhile, has been confirmed as presenting SymbiFlow, a project which aims to be the equivalent to the GNU Compiler Collection (GCC) for field-programmable gate arrays (FPGAs).

Other confirmed speakers include: Julius Baxter on Morse Micro’s adaptation of the Rocket RISC-V core generator for single-chip 802.11ah use; Charles Papon, creator of the Scala-based SpinalHDL hardware description language project; Ben Reynwar on Python as a language for testing and code generation as found in FuseSoC and its generators; Germán Cano Quiveu on booting OpenRISC system-on-chips via a Wi-Fi-enabled open bootloader; Philipp Wagner on the Open SoC Debug (OSD) specification and the LibreCores project; and Dan Gisselquist on the lessons learned while formally verifying the ZipCPU design.

Hosted by the Gdansk University of Technology, ORConf 2018 takes place between from the 21st to the 23rd of September. More information is available on the official website.

Popular open-source electronic design automation (EDA) package KiCad has hit its milestone 5.0.0 release, described by the team as “a new generation” of the software.

“Almost a year after the release of KiCad 4.0.7, the KiCad development team is proud to present a new and improved KiCad 5.0 release,” the project’s maintainers announced over the weekend, confirming the launch of the first stable build from the new 5.0 branch.

The list of changes since the 4.0 branch is impressive: new libraries for symbols, footprints, and 3D models all adhering to the KiCad Library Convention (KLC); a new 3D view and model plug-in architecture with STEP and IGES support; arbitrary colour scheme support; better high-resolution display support; the ability to directly import projects made in Eagle into KiCad; SPICE simulation in Eeschema; improved modern canvas in PcbNew; the first support for modern canvas in GerbView; new measurement tools; and more.

Full details, and links to download precompiled binaries and the project’s source code, can be found on the official KiCad website.

Bootlin has announced the delivery of all the main goals from its crowdfunding project to create an upstream-compatible open driver for the popular Allwinner visual processing unit (VPU) hardware found in many embedded designs.

Funded via Kickstarter, the campaign by Bootlin engineer Maxime Ripard and intern Paul Kocialkowski saw efforts to create a fully open driver for accelerated media via the Allwinner VPU – something Allwinner itself has not provided – which could be upstreamed into the Linux kernel proper, making Allwinner-based platforms more accessible to open-source and free software projects.

In its latest announcement, Bootlin has confirmed that the majority of the goals set by the campaign have been completed: a driver, Cedrus, is now available on a range of Allwinner system-on-chip (SoC) designs, including older models like the A10 and H3, with MPEG2 and H264 hardware-accelerated decoding, direct video display, and the creation of a user-space library for integration into open-source video players – though this is only partially met at present, having been showing to be compatible with the popular Kodi media player but not yet completed for other software including VLC and GStreamer.

Finally, progress is being made to upstream the driver and library packages for out-of-the-box use in future Linux kernels, though the provided patches have not yet been merged.

More information is available on the Bootlin blog post.

IBM and Microsoft have begun efforts to develop the next generation of programming talent for the impending era of quantum computing, focusing on gamified core concepts and practical programming katas respectively.

Unlike traditional computers, which – with some notable exceptions – use binary bits with an on-off state, quantum computers use qubits which can be in both states at the same time. These quantum systems, researchers promise, can carry out selected workloads with considerably more efficiency than binary computers, which is why there’s little surprise to see some of the big names in the industry putting their weight behind the concept.

IBM is among these, having published a game for Android and iOS mobile devices dubbed Hello Quantum. Based on the company’s Q Experience quantum computing education programme, and described in detail by Dr. James Wootton in this Medium post, Hello Quantum is a game designed to introduce the concepts behind qubit-based quantum computing. Starting with the simplest system, a single qubit, the game gets progressively more challenging as additional qubits are added to the quantum system.

Microsoft, meanwhile, has published a series of quantum computing katas under the permissive MIT licence as a means of both educating programmers as to the concepts behind quantum computing and providing hands-on experience of its in-house quantum programming language Q#. The initiative currently covers four key topics: basic single- and multi-qubit quantum computing gates; quantum superposition, where a qubit is said to hold both 0 and 1 values simultaneously; distinguishing quantum states using measurements; and the writing of quantum oracles based on the Bernstein–Vazirani and Deutsch–Jozsa algorithms.

IBM’s Hello Quantum game is available on the Google Play Store and the iTunes App Store now as a free download; Microsoft’s Q# katas can be found on the project’s GitHub repository.

RISC-V Foundation director Ted Speers has offered up more details on the organisations he would like to see involved in the recently-announced Security Standing Committee.

Announced earlier this month by executive director Rick O’Connor, the RISC-V Foundation’s Security Standing Committee came with a request: “[A] call to action for industry leaders, universities and government organisations to join the Foundation and work with us to build a more secure world for the benefit of everyone.”

Now, Foundation director Ted Speers has offered more details of whom the Committee is looking towards to help ensure the security of both the RISC-V instruction set architecture (ISA) and the wider industry.

“I would like to make an appeal for new members to join the RISC-V Foundation and the Security Standing Committee to become involved in developing better security practices and solutions, which is fundamental to every business in our industry,” Ted writes as part of an in-depth look at the Committee’s founding. “In addition to participation from security companies, we’d also like participation from the big data giants and defence companies. If you’re reading this and are excited about this opportunity to build a more secure world, reach out to the Foundation to get involved.”

More information on the Committee is available on the official website.

Finally, Google has announced plans to release a hardware product, dubbed Edge TPU, to bring its TensorFlow-accelerating Tensor Processing Unit (TPU) technology to the Internet of Things.

Originally announced back in May 2016 as an internal project to accelerate the company’s search, translation, and other services, the Tensor Processing Unit is a family of custom-built application-specific integrated circuit (ASICs) designed to accelerate deep-learning algorithms. From its internal-use-only unveiling, the technology has made its way to the Google Cloud platform – and now, for the first time, will be made available in hardware form for third-party developers.

“Edge TPU is Google’s purpose-built ASIC chip designed to run TensorFlow Lite ML models at the edge,” says Injong Rhee, vice president for Internet of Things (IoT) and Google Cloud at the advertising giant. “When designing Edge TPU, we were hyperfocused on optimising for ‘performance per watt’ and ‘performance per dollar’ within a small footprint. Edge TPUs are designed to complement our Cloud TPU offering, so you can accelerate ML training in the cloud, then have lightning-fast ML inference at the edge. Your sensors become more than data collectors – they make local, real-time, intelligent decisions.”

Google has confirmed partnerships with a range of companies to integrated Edge TPU hardware into their products, while also promising to release a system-on-module (SOM) development board, similar in layout to the popular Raspberry Pi, for developers interested in experimenting with the acceleration hardware.

More information is available from Injong’s announcement post and the product page, where developers can request early access to the Edge TPU hardware itself.