The maintainers of the Wishbone interconnect specification are calling for input on its future evolution, after converting the specification into an editor-friendly format for ease of participation.

Offering eight, 16, 32, and 64 bit widths and originally created by the Silicore Corporation before being released under a permissive licence, the Wishbone bus is a popular choice for cross-core interconnections in free and open source silicon designs. Its maintainers, though, are looking to evolve the standard – and are calling for assistance in doing so.

“Tristan and I have converted the Wishbone spec into a more editor-friendly format (rst). Tristan has thankfully already reviewed the document and you can find the current release candidate for the 3.1 in the GitHub repository,” writes Stefan Wallentowitz on the LibreCores mailing list. “Please suggest changes via PRs in the next three weeks. You can also create a placeholder PR and fill it later to raise a concern or feature. Generic discussion should probably be on this mailing list.”

The call goes out to more than just those looking to revise the specification directly, too. “I would love to have supporting material released along the new spec,” Wallentowitz continues, “like formal models, updated cocotb models, standard bus bridges etc. Contributions are highly welcome!”

Those interested in providing input on the next Wishbone standard can participate via the GitHub repository and the LibreCores mailing list.

The free and open source silicon movement is continuing to capture mainstream interest, with The Economist becoming the latest publication to examine the impact the movement is having both generally and in specific cases.

There’s a temptation to view free and open source silicon purely in terms of economic value to established ventures, where companies like Western Digital and Nvidia can cut a considerable cost from their bottom line by investing in customised silicon based on open instruction set architectures in place of off-the-shelf proprietary cores. Doing so, however, ignores a bigger aspect: the potential impact it has on enabling those who had previously been excluded from the industry to get a foothold with a far, far lower barrier to entry than ever before.

The Economist is the latest in a string of mainstream publications switching on to the potential for free and open source silicon, and has launched a trio of articles beginning with a look at how India is using FOSSi technology to kickstart a native chip-building industry. It’s an effort we’ve covered in the past: A 2015 OSDDI interview introduced Arjun Menon and Rahul Bodduna and the SHAKTI project they were working on at IIT Madras, which had progressed by November 2017 to targeting manufacturing in early 2018. By August 2018 Linux was booting on a SHAKTI test chip produced by Intel Corporation and HCL Technologies on a 22nm process; just two months later the project had switched to a 180nm test chip manufactured within India’s borders. Since then, the project has enjoyed considerable interest from the international semiconductor industry – including a partnership with Thales to produce a fault-tolerant version.

A second Economist article dives into the RISC-V instruction set architecture itself, describing the impressive progress made in bringing RISC-V parts to market over the last year as “a boomlet” which if it becomes a boom “may change the chip industry dramatically, to the detriment of Arm and intel, because unlike the ISAs from those two firms, which are proprietary, RISC-V is available to anyone, anywhere, and is free.”

The Economist’s final feature discusses the rise of open-source computing, described as “a striking success” in the software field which is now extending to the processor in a move which it claims could calm tempers between China’s growing technology industry and the west’s incumbent industry – a “battle for influence [which] would be extraordinarily costly and force most countries to take sides” should it boil over, the publication claims, while “open-source computing can help calm tempers [which] would be good for everybody.”

While the Economist’s interest in the field is welcome, it’s not the first mainstream publication to see the free and open source silicon movement as worthy of coverage: In 2017 Raconteur interviewed industry experts, including AB Open’s own Andrew back, for its Future of Manufacturing report, first published in The Times and now available for download on the Raconteur website.

Cambridge-based has announced £2.7 million in funding, with which it plans to accelerate its roll-out of Internet of Things (IoT) maintenance and update platform FoundriesFactory.

Founded in 2017, launched after a stealth period of just under two years with the announcement of Linux and Zephyr real-time operating system (RTOS) ‘microPlatform’ distributions offering continuous updates for the embedded, IoT, edge, and automotive industries. “ has been the leader in making Zephyr available as a continuously updated microPlatform distribution,” said Kate Stewart, Senior Director of Strategic Programs at the Linux Foundation, at the time.

Now, has closed a £2.7 million round of funding, with plans to use the money to accelerate the roll-out of its FoundriesFactory commercial maintenance offering.

“Building today’s IoT & Edge devices requires more than just an OS – delivers a flexible software solution for development, testing, deployment and maintenance of IoT devices,” claims chief executive George Grey. “Our commercial FoundriesFactory solution enables customers to customise and future proof their products using an innovative subscription-based lifetime model. There is no lock in, no access to our customers’ data, and no per unit costs. With Crane Venture Partners and Backed VC we have investors who share our vision on the impact we can deliver with a unifying software platform for the IoT market.”

“Our goal at Crane is to invest in companies that are going to revolutionise large addressable markets,” adds Krishna Visvanathan, founder of round lead Crane Venture Partners. “ offers a disruptive approach to solving the key issues affecting the IoT space, including security and implementation. They have already delivered value and validated their approach with their initial customers and are seeing their open source approach as key to adoption for this market.”

More information on is available from the official website.

The free and open OpenPiton+Ariane heterogeneous research processor is now available on Amazon’s Elastic Compute Cloud (EC2) field-programmable gate arrays, providing an easy route to test it out without needing dedicated hardware.

A partnership between the PULP Platform and the OpenPiton project released back in December last year, OpenPiton+Ariane combines the OpenSPARC and RISC-V cores to build what its creators call “the ideal permissive open-source RISC-V system that scales from single-core to many-core.”

Now, OpenPiton+Ariane is available on Amazon’s Elastic Compute Cloud (EC2) for the first time – allowing developers and tinkerers to get started without the need for dedicated hardware.

“OpenPiton release 13 (19-10-23-r13) is now available. The headline feature of this release is support for running OpenPiton+Ariane in the cloud via Amazon EC2 F1,” OpenPiton’s Jonathan Balkind announced late yesterday. “We now provide a step-by-step guide in the README of OpenPiton on GitHub which explains how to emulate OpenPiton+Ariane on Amazon EC2 F1 cloud FPGAs. You can make use of our existing release image to test software and firmware, or synthesise your own OpenPiton-based hardware design by following our instructions.”

The latest OpenPiton Release, 13, is available on the project’s official website; instructions for getting started on Amazon EC2 can be found on the OpenPiton GitHub repository.

The organisers of the RISC-V Devroom at the FOSDEM 2020 conference, taking place in Brussels this coming February, have opened the call for talk proposals.

“FOSDEM 2020 will take place on February 1-2, 2020 in Brussels, Belgium. There will be a half day RISC-V developer’s room on February 1st (Saturday),” writes Arun Thomas in a message to the RISC-V Foundation’s software mailing list. “The topic of the devroom encompasses the RISC-V ISA, open source RISC-V hardware (e.g. cores, SoCs, accelerators), and open source RISC-V software (e.g. OS ports, emulators).

“The default duration for talks will be 45 minutes including discussion. Feel free to request a longer or shorter slot. Presentations will be recorded and streamed. Sending your proposal implies giving permission to have your presentation recorded and distributed under a Creative Commons CC-BY licence.”

Those interested in participating are requested to submit a title, subtitle, one-paragraph abstract and optional more detailed description via the event website no later than the 24th of November. Full details on FOSDEM 2020 itself, meanwhile, can be found on the official website.

The RISC-V Foundation has announced the agenda for its second annual RISC-V summit, taking place this December in San Jose, California.

“The RISC-V Foundation, in partnership with Informa’s Tech Division, is hosting its annual RISC-V Summit, a four-day conference featuring keynotes, smaller breakout sessions, tutorials, exhibitions and networking receptions, as well as member meetings to open the week’s events,” the Foundation explains. “Leading technology companies and research institutions will share notable product updates, projects and implementations and discuss how the RISC-V ISA is driving the next generation of hardware, software and IP. The keynotes for the RISC-V Summit will include representatives from Arm, IBM, Microchip, OpenHW Group, SiFive, and Western Digital.”

The event is, as with the RISC-V Summit 2018, split into closed and open sessions. The first day of the event, Monday the 9th of December, is open only to Foundation member companies; the Tuesday and Wednesday sessions are open to all with keynote speakers in the mornings and breakout sessions in the afternoon; finally, an open workshop day on the Thursday features technical tutorials and investigations into real-world RISC-V usage.

Confirmed speakers include RISC-V Foundation chief executive Calista Redmond, SiFive’s Krste Asanovic, Western Digital’s Martin Fink, Microchip’s Ted SPeers, SiFive’s Yunsup Lee, RISC-V Foundation vice-chair David Patterson, Red Hat’s Wei Fu, Embecosm’s Jeremy Bennet, NXP’s Joe Circello, and FreeRTOS’ Ricahrd Berry, as well as a talk by Google’s Richard Ho and Tao Lui on open-source verification for RISC-V processors.

The full schedule, including registration links, can be found on the event website.

CHIPS Alliance has opened registration for a two-day open-source design verification workshop, taking place on the 14th and 15th of November in Munich, Germany.

Launched back in March, CHIPS Alliance is a Linux Foundation project focused on supporting the burgeoning free and open source silicon (FOSSi) movement. Its first official workshop was held back in June at the Google Sunnyvale campus, and now the organisation has announced its second will take place in November at the Munich University of Applied Sciences.

“CHIPS Alliance and Munich University of Applied Sciences are organising a workshop [on] Open Source Design Verification in Munich on 14-15 November 2019,” Prof. Stefan Wallentowitz announced on the organisation’s announcement mailing list. “It is open to everyone to attend and many projects from the CHIPS Alliance ecosystem will be presenting.”

The workshop’s presenters will be gathered from industry, academia, and the hobbyist sectors, with topics on offer including – but, the organisation points out, not limited to – open source simulation tools, design verification tools, rapid prototyping tools and methodologies, libraries for design verification, open standards, and industry case studies demonstrating real-world usage of all of the above.

More details on the workshop can be found on the CHIPS Alliance website.