It’s been a strong fortnight for machine intelligence fans, starting with Arm’s Robert Elliot and Mark O’Conner publishing a white paper on the company’s Arm NN machine learning platform and its optimisations for use on low-power embedded devices.

“We expect machine learning to become a natural part of programming environments, with tiny embedded neural networks being part of program execution,” the pair explain of the inspiration behind Arm NN. “To prepare for this, we’ve developed a low-overhead inference engine with the ability to import a file produced by a handful of machine learning frameworks. This supports a ‘write once, deploy many’ approach to development, with the same framework able to target the Cortex-A class cores used in high-end mobile as well as the Cortex-M class cores used in processing environments with very small memories. We’ve spent significant effort to make sure that good performance is achieved on all of these processors

“Arm NN bridges the gap between existing frameworks and the underlying Arm IP. It enables efficient translation of existing neural network frameworks, including TensorFlow and Caffe, allowing them to run efficiently, without modification, across Arm processing platforms. The inference engine can be distributed to different devices while taking advantage of the key optimizations of each.”

In the paper’s practical example, Robert and Mark demonstrate the importation of a TensorFlow file and its subsequent optimisation for embedded devices, while promising that ongoing optimisations will allow for seamless cloud-to-edge deployment, improved heterogeneous scheduling, and better compiler tools which simplify arithmetic sequences and reduce memory access and bandwidth requirements.

The paper is available following free registration on the official Arm website.

Qualcomm, meanwhile, has announced the launch of a new family of Internet of Things (IoT) focused system-on-chips (SoC) with embedded image signal processing and artificial intelligence capabilities, the first in a new range of parts for what it calls the Qualcomm Vision Intelligence Platform.

“Our goal is to make IoT devices significantly smarter as we help customers bring powerful on-device intelligence, camera processing and security. AI is already enabling cameras with object detection, tracking, classification and facial recognition, robots that avoid obstacles autonomously, and action cameras that learn and generate a video summary of your latest adventure, but this is really just the beginning,” says Joseph Bousaba, vice president of product management at Qualcomm. “The Qualcomm Vision Intelligence Platform is the culmination of years of advanced research and development that brings together breakthrough advancements in camera, on-device AI and heterogeneous computing. The platform is a premier launchpad for manufacturers and developers to create a new world of intelligent IoT devices.”

Initially available in two models – the QCS603 with 64-bit four-core big.LITTLE Kryo CPU running at 1.7/1.6GHz and the QCS605 with eight-core Kryo CPU running at 2.5GHz/1.7GHz – the new SoCs include a neural processing engine offering 2.1 trillion operations per second (TOPS) in a 1W power envelope, a Qualcomm Hexagon 685 Vector Processor digital signal processor (DSP), Adreno 615 GPU, dual 14-bit Qualcomm Spectra 270 image signal processors (ISPs), and are built on a 10nm low-power process.

The parts are sampling now, the company has confirmed, with Kedacom and Ricoh Theta named as the first customers to be building products around the new platform. More information is available on the official website.

The team behind postmarketOS has written of initial progress in porting OsmocomBB, an open GSM mobile baseband, to more modern and readily-available hardware – paving the way to a fully open GSM stack running on a mobile handset.

“There is already a free software implementation of a GSM baseband called OsmocomBB. But it is only compatible with phones based on the TI Calypso chipset, such as the Motorola C138,” the team explains in a blog post. “Given that the Motorola C138 came out in 2006 and is no longer produced, OsmocomBB’s use is limited unless it gets ported to newer platforms.”

Developer “unrznbl” has begun porting OsmocomBB to Fernvale, a development platform based on the Mediatek MT6260 and which opens many of the chip’s otherwise closed and proprietary features. Using a Fernvale board, the full Osmocom GSM stack can be implemented – with the current Calypso-based version supporting only the Layer 1 portion, requiring communication via serial cable to external hardware for the other layers.

“After the entire layer one firmware of OsmocomBB is ported to Fernvale, it would be possible to do 2G voice calls, send SMS and access the Internet from a laptop via tethering (just like it is possible with old Motorola phones today). @unrznbl is also involved in creating layer one as a library for use in NuttX, bringing full userspace phone functionality to it,” the postmarketOS team continues. “With this, in combination with an oFono or RILD compatible interface added to the code, postmarketOS and friends, would be able to talk to the cellular modem inside the phone. All without the rather inconvenient laptop in between.”

While the process is still at a relatively early stage, opening of the stack on readily-accessible hardware in this manner could have major impacts not only in the maker and tinkerer communities at which postmarketOS is targeted but also for high-security and highly-sensitive applications where a fully open GSM stack would offer heightened security, privacy, and accountability.

On the RISC-V front Rambus has become the latest company to adopt the open instruction set architecture (ISA), using its openness as the basis for a new embedded and Internet of Things (IoT) security core dubbed the CryptoManager Root of Trust.

“The fundamental pillars of architectural design freedom, secure processing siloed away from general processing, and layered security with a root of trust designed for multiple security layers, are unique to the CryptoManager Root of Trust design and enable easy implementation with the highest levels of protection,” Bret Sewell, senior vice president and general manager of Rambus’ security division, explains of the new core design. “The CryptoManager Root of Trust also embeds features that enable semiconductor manufacturers and device OEMs to insert hardware keys, and enables IoT service providers to manage IoT endpoints throughout their lifecycle in the field.”

Rambus’ decision for picking RISC-V over proprietary rivals, the company claims, centres primarily around its open nature allowing for the design of a custom processor built with security in mind from the ground up and with a guarantee that there are no back-doors, intentional or otherwise, which could be included with closed-source proprietary cores.

“The Meltdown and Spectre flaws revealed a new class of vulnerabilities as common processors employ acceleration techniques like speculative execution to improve processing performance,” adds Rick O’Connor, executive director of the RISC-V Foundation. “With solutions like the Rambus CryptoManager Root of Trust, the extensible RISC-V ISA enables developers to build connected products with a fundamentally more robust approach to security.”

Details on the CryptoManager Root of Trust are available from Rambus’ website.

Finally, the open-source seL4 microkernel, the first general-purpose kernel to have been proven to-spec using formal verification methods, has been ported to RISC-V – though its creators warn it’s in a very early, limited form.

Originally developed by Australia’s National Information and Communications Technology (ICT) Research Centre of Excellence (NICTA) and now under the stewardship of Data61’s Trustworthy Systems Group, the seL4 microkernel is a security-focused offshoot of the high-performance L4 microkernel developed by Jochen Liedtke. Already available for Armv6, Armv7, and x86 instruction set architectures, the microkernal’s latest release – seL4 v9.0.1 – comes with initial RISC-V support, though in prototype form.

“RISC-V, through its openness and greenfield design, provides an opportunity for re-thinking the hardware-software stack. The open architecture, which is designed by leading architects and has strong industry support, is an ideal platform for our open-source seL4 system,” Data61’s Professor Gernot Heiser explains in a statement to Computerworld on the port. “We anticipate the combination of seL4 and RISC-V to provide a compelling security solution for the next-generation Internet of Things and cyber-physical systems.”

The prototype release currently supports only 64-bit RISC-V without floating-point unit (FPU) and multicore support on the Spike simulation platform, though extended support is expected to follow in future releases. Data61 has warned that the RISC-V port currently has no verification, unlike the microkernel’s other ports. More information is available on the release page.