Technology journalist Gareth Halfacree is running the AB Open Community Round-Up series, offering a fortnightly glimpse at what’s happening in and around open source hardware and software, wireless and related topics.

RISC-V-based microcontroller creator OnChip has a convincing reason to investigate its Open-V crowdfunded hardware, courtesy its latest campaign update: the company is working on developing entirely open analogue blocks.

Traditionally, microcontrollers which need analogue circuitry – anything from analogue-to-digital conversion (ADC) to clock generation and distribution – have to licence proprietary IP owing to the complexity of designing such peripherals. As your project gets more complex – such as microprocessors with the need for a DDR PHY to connect to high-speed memory – the amount of expensive black-box IP in your ‘open’ design only increases. Open-V is looking to change that, working towards having entirely open analogue peripherals running alongside its implementation of the open RISC-V architecture processor core.

“We are one of the only groups actively working to create open and understandable analogue blocks,” the Open-V team claimed in its most recent update. “Analogue peripherals are the last major barrier to truly free microcontrollers. We’re tackling that problem head-on.” The project has 21 days left to reach its $480,000 funding goal on Crowd Supply.

In more good news for RISC-V fans Jean-Paul Etienne has announced a port of the Zephyr real-time operating system (RTOS) to the architecture, supporting in its initial release the SiFive machine model in the Qemu emulator and the Pulpino microcontroller.

Designed specifically for use on resource-constrained devices, the open-source Zephyr RTOS has been written to be easily ported to new architectures and platforms. The port adds another tally mark to a growing list of kernels and operating systems boasting support for RISC-V platforms.

Jean-Paul has released the source code for his port to the Zephyr Project for review, and plans to adds support for the SiFive Freedom E310 SoC in a future update.

Newport-based GCell has announced its first LoRa wireless sensor node to be powered entirely through harvested energy, using the company’s indoor photovoltaic solar panel technology to power the transmission of readings over a LoRa network every fifteen minutes.

Developed in partnership with Professor Marcel Meli at the Zurich University of Applied Sciences Institute of Embedded Systems (ZHAW) and based on the company’s previous work with Bluetooth beacon systems, the energy harvesting nodes are claimed to neither require battery maintenance nor replacement once deployed in the field.

GCell has confirmed plans to run a trial of its LoRa nodes in early 2017, while more information on the technology behind them can be found in Marcel Meli and Philipp Bachmann’s paper on the project.

Google has taken its Project Brillo platform out for a lick of paint, and it has come back with a shiny new name and an improved feature list: Android Things.

Building on the work done on Brillo, launched around a year ago, Android Things is claimed to make it easier to build Internet of Things (IoT) projects for developers with experience of the Android ecosystem. In particular, Android Things supports devices with and without displays, the Android Studio and Software Development Kit, and can link directly into Google Play Services and the Google Cloud Platform.

The initial release of Android Things includes board support packages (BSPs) and pre-built operating system images for development platforms including the Raspberry Pi 3, the Intel Edison, and the NXP Pico.

Finally, anyone thinking of or currently developing on ARM’s Cortex-M0 family should head over to to check out detailed extracts from Joseph Yiu’s The Definitive Guide to ARM Cortex-M0 and Cortex-M0+ Processors.’s coverage of the book concentrates on the chips’ suitability for extremely low-power projects. While representing only a small portion of the book, the site’s extracts include useful tips and guides on using the low-power states of the chips, benchmarking for power consumption, and waking the chips when required.

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