SHAKTI is an open-source processor program based on RISC-V ISA and is an academic initiative started in 2014, by Reconfigurable Intelligent Systems Engineering (RISE) Group in IIT-Madras. The motivation of the SHAKTI project was to create an open-source processor ecosystem, to increase collaborations between academia and industry. The program aims to include open-source production grade processors, SoCs, and even development boards.
The SHAKTI processors and front-end design use high-level synthesis language, Bluespec System Verilog (BSV). The processors are categorized as Base processors, Multi-core processors, and Experimental processors. The first indigenous processors were Embedded Class (E-Class) and Controller Class (C-Class), which were aimed at the Internet of Things, embedded, and desktop applications. The Base class of processors includes E-Class, C-Class, and I-Class; Multi-core processors include M-Class, S-Class, and H-Class; and Experimental processors includes T-Class and F-Class. The SHAKTI project incorporates 6 processors based on RISC-V ISA. The third and most recent successful silicon tape-out was Moushik, which is an Embedded Class (E-Class) core. The IP sources for the SHAKTI ecosystem are open-sourced under a 3-Clause BSD License.
Processor classes
E-arty35T is an SoC built around Embedded Class (E-Class), which is a 32/64-bit microcontroller based on RISC-V ISA. The E-Class processor is compared against ARM’s M-class cores. It is an in-order 3 stage pipeline having an operational frequency of less than 200MHz. The E-Class runs on Real-Time Operating Systems (RTOS), Zephyr OS and FreeRTOS. The E-arty35T is a 32-bit E-Class microcontroller with 128kB RAM and 32 GPIO pins, Platform Level Interrupt Controller (PLIC), Counter, 2x Serial Peripheral (SPI), 2x Universal Asynchronous Receiver Transmitter (UART), 1x Inter-Integrated Circuit (I2C), 6x Pulse Width Modulator (PWM) and Xilinx Analog-Digital Converter (X-ADC).
C-arty100T is an SoC built around Controller Class (C-Class), which is a 64-bit microcontroller based on RISC-V ISA. C-Class is targeted at mobile applications and can run at up to 1.5 GHz. It has 16x GPIO pins, 1x PLIC, 1x UART and 1x I2C. Two tape-outs of C-Class processors are the RIMO and Risecreek test chips.
I-Class is a superscalar out-of-order (OoO) processor with potential applications in general-purpose computing and high-end embedded applications. Implementation is once again via Bluespec System Verilog, with verification, and performance analysis ongoing.
M-Class is the mobile class processor with a maximum of 8x cores and is the combination of C-Class and I-Class cores. TileLink is used for cache-coherency, along with transaction adaptors to AHB/AXI4 to connect peripherals. It is expected that the core complex of 2 or 4 will share an L2 cache, and L3 caches are an option and usually used in desktop type applications.
S-Class is aimed at workstations or enterprise server workloads. The base core is essentially the advanced version of I-Class with quad-core and multi-threading support. Even in this class of processors, TileLink is used as cache-coherent mesh fabric. A maximum of 32 cores can be supported.
H-Class is targeted for highly parallel enterprise, high-performance computing (HPC), and analytics workloads. The core is again a combination of C-Class and I-Class, with single-thread performance driving the core choice. Optional L4 cache and optimized memory hierarchy are available to achieve high memory bandwidth. The architecture thrust is on accelerators, VPU and AI/ML, for up to 128x cores and with multiple accelerators per core.
T-Class is a variant of C-Class and is an experimental class of processors for object-level security. It is designed to support coarse and fine grain tags. Coarse grain tags can be used to realize micro virtual machine-like functions to mitigate software attacks.
F-Class is the fault-tolerant version of the base class processor, which includes redundant compute blocks such as dual modular redundancy, triple modular redundancy, temporal redundancy modules to detect permanent faults, ECC for circuit memory blocks, and many more techniques that are used for fault tolerance.
Tapeouts
HCL’s daughter board containing the processor
SHAKTI project first announced its success in booting Linux on a home-grown RISC-V based processor back in 2018. It was fabricated on 22nm FinFET, running at 400MHz and benchmark of 1.67 DMIPs/MHz. Following which the chip was built in India on a 180nm node at the ISRO Semiconductor Laboratory in Chandigarh. It was subsequently commercialized by a start-up called InCore Semiconductors. It becomes the second to successfully boot Linux on the RISC-V processor, following after SiFive.
RIMO is an entirely open source SHAKTI C-Class SoC, that has been taped out at Semi-Conductor Laboratory at Chandigarh using 180 nm process technology. The core runs at 1.68 DMIPs/MHz. It is an in-order 5-stage 64-bit microcontroller supporting RISC-V ISA (RV64IMAFD). It is compatible with user spec (2.2), privilege spec (v1.10) of RISC-V ISA, and supports the sv39 virtualization scheme. It comes with 2x UART, 2x I2C, 1x JTAG debugger, and 256KB memory, 32x GPIOs. It supports FreeRTOS.
RIMO SoC
Risecreek is again one more C-Class based SoC, that was taped out at Intel, Oregon USA, using 22 nm process technology. The chip operates at frequencies of up to 350 MHz and runs at 1.68 DMIPs/MHz. It is a 5-stage in-order, 64-bit microcontroller and uses RV64IMAFD. It comes with 1 64-bit SDRAM from open-cores, 2 QSPI, 2 I2C, tightly coupled memory 128KB, 1 JTAG Debugger, 32 GPIOs, 1 DMA compatible with AXI-4, 1 UART. It is an open-source design and made freely available.
Risecreek SoC
In September 2020, the SHAKTI team has announced its third and youngest physical chip “Moushik”. It is SHAKTI E-Class RISC-V core built on a 180nm process technology. It comes with 103x input/output (IO) pins across a 256-pin package. The CPU runs between 75MHz and 100MHz, while the SoC includes several common peripherals, including an SDRAM controller, I2C, quad-SPI, analog-to-digital conversion (ADC), UART, and JTAG for debugging.
Moushik SoC
Software support
Along with a comprehensive family of processors, SHAKTI also provide a wide range of system software and toolchain support. There are software development kits (SDKs) and an integrated development environment (IDE). The main objective of SHAKTI-SDK is to reduce development time. Debug codes and board support libraries are also provided. This eases the development process for SHAKTI processors, while being simple and customizable as well. SHAKTI-SDK is C/C++ platform that provides firmware code and a framework to develop applications for the hardware.
A bright future
Chip design and fabrication, test PCB design and manufacture, along with post-silicon boot-up and testing has all been done natively within India, creating huge potential for a powerful processor industry that is based in India.
The SHAKTI program is largely funded by the Ministry of Electronics and Information Technology, Government of India, which also makes it popular among academia and industry. The government of India has launched the Swadeshi Microprocessor Challenge under #AatmaNirbharBharat Abhiyan (Self-reliant India Program). This program builds upon RISC-V based processors from SHAKTI, C-DAC, making it more available to startups and academia to develop their own applications on these processors. SHAKTI has the potential to become India’s most successful SoC natively designed, fabricated to post-silicon boot-up for industry-grade applications.
Abhishek Jadhav is a senior undergraduate Electronics and Telecommunication engineering student and technical author. As an RISC-V Ambassador he represents them at global level, being the first Indian and only student. He leads an Open Hardware Developer Community across India with more than 80 students. Abhishek is 5G enthusiast and its implementation in Smart Cities and AIoT.