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CRU: RISC-V Growth, Job Vacancies, and More

Cambridge-based semiconductor specialist UltraSoC has announced its expansion into Bristol, and it’s giving credit for its recent growth to an explosion of interest in the open-source RISC-V instruction set architecture (ISA). “There’s a perfect storm of factors revolutionising the technology business from top to bottom,” says Rupert Baines, UltraSoC’s chief executive, of the changes he…

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LoRaWAN Bat Detector

CRU: LoRa Bat Watching, RISC-V Updates, Neural Networks, and More

AB Open’s Andrew Back has written up a project to create a bat detector with LoRaWAN connectivity, transmitting data on bat call measurements via The Things Network using MQTT. “When ODI Leeds recently said that they were interested in LoRaWAN-enabled bat detection, we thought, ‘What a fun idea, let’s have go!’,” writes Andrew of the…

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OSDDI: lowRISC, Alex Bradbury

lowRISC is a fantastic initiative to build a fully open source, Linux-capable, 64-bit RISC-V based system-on-chip. Not only this, but a SoC design with additional interesting features such as programmable I/O — think along the lines of XMOS devices — and tagged memory.

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OSDDI: OpenRISC, Olof Kindgren

The OpenRISC processor has been around for a good number of years and it has found use in a NASA satellite and Samsung digital televisions, to name just two applications. In this instalment of Open Source Digital Design Insights, long time OpenRISC contributor and open source developer, Olof Kindgren, provides an introduction to the project,…

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Wuthering Bytes 2017

With Gareth on vacation there’s no Community Round-Up this fortnight, so I thought I’d take the opportunity to provide a rundown on what we have in store for the annual  Wuthering Bytes technology festival — running over 10 days again! — that will get off to a start in just a few weeks time. Festival…

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OSDDI: SHAKTI Processor, IIT Madras

This latest instalment of Open Source Digital Design Insights is once again from interviews filmed back at ORConf 2015 in Geneva, and this time on the RISC-V based SHAKTI processor from IIT Madras. A project that aims to build 6 processor variants that range from microcontroller up to HPC class silicon, with processor interconnect and…

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Calderdale's LoRaWAN Gateway

CRU: LoRaWAN fun, RISC-V education, FPGAs, and more

AB Open’s Andrew Back has written of our work on a LoRaWAN gateway for the region, installed on an iconic 275-feet tall landmark with intermittent power. Part of AB Open’s participation in the IoTUK Boost programme, the installation is designed to provide connectivity to The Things Network’s long-range radio wide-area network (LoRaWAN) as Things Calderdale….

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SiFive RISC-V processor

CRU: RISC-V Toolchains, Tiny PCBs, 6502-as-a-Service, and More

Developer Liviu Ionescu has published the results of RISC-V toolchain testing, comparing the GNU MCU Eclipse toolchain to the GCC-based toolchain from SiFive across four configurations. “After releasing GNU MCU Eclipse RISC-V Embedded GCC, I tested if the strategy used while building it is effective,” Liviu explains of his experiments, which saw the SiFive example…

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