Storage giant Western Digital has officially released the source code for its SweRV RISC-V core, under the permissive Apache 2.0 Licence, allowing anyone to run, experiment with, or modify its implementation.

Announced back in December, SweRV is a RISC-V core implementation developed in-house as part of Western Digital’s aim to transition its storage processing products away from proprietary cores and onto the free and open instruction set architecture (ISA). “Our SweRV Core and the new cache coherency fabric initiative demonstrate the significant possibilities that can be realised by bringing data closer to processing power,” claimed WD chief technology officer Martin Fink at the time. “These planned contributions to the open-source community and continued commitment of the RISC-V initiative offer exciting potential to accelerate collaborative innovation and data-driven discoveries.”

The announcement came without any source code for the core, though WD did release a simulator called Whisper for those eager to get started with SweRV development. Now, the company has made good on its promise with the release of full SweRV source code.

Uploaded to the company’s official GitHub repository late last week, the release includes register transfer level (RTL) code in Verilog format for the core, along with a quickstart guide for configuring and building a model in Verilator, Synopsys, and Cadence targets. All are covered under the Apache Licence 2.0, a permissive licence supporting distribution with or without modification for personal or commercial use, while also including an express grant of patent rights where applicable.

The code can be downloaded now from Western Digital’s GitHub repository.