The lowRISC project has announced the release of version 0.6 of its open silicon offering, bringing improvements to performance, debugging, and network connectivity – alongside a pledge to add alternative RISC-V cores to the current Rocket option.
Ten months after the release of lowRISC 0.5 brought initial support for Ethernet connectivity, lowRISC’s 0.6 milestone release offers a wealth of improvements. “This release includes an updated version of the Rocket RISC-V core, a higher core clock frequency, JTAG debugging support, Ethernet improvements, and more,” explains developer Alex Bradbury of the project’s progress since January. “We’ve also taken the opportunity to re-organise our documentation, adding an easy to follow quick-start guide.”
From here, the team is looking at shifting away from a pure focus on the Rocket RISC-V processor core by offering an additional choice to its users: “Our next development focus is to add support for dropping in the Ariane RISC-V design, from ETH Zurich,” Alex explains, “as an alternative to Rocket.”
The new getting-started tutorial can be found on the documentation website, while lowRISC 0.6 itself is available from the project GitHub repository.
Gareth Halfacree is a technology journalist and technical author best known for his work on the Raspberry Pi User Guide and an upcoming book covering the BBC’s micro:bit project. A keen open source advocate and RISC-V fan, Gareth is responsible for curating our fortnightly community round-up posts.