Segger J-Link

CRU: RISC-V Growth, Job Vacancies, and More

Cambridge-based semiconductor specialist UltraSoC has announced its expansion into Bristol, and it’s giving credit for its recent growth to an explosion of interest in the open-source RISC-V instruction set architecture (ISA).

“There’s a perfect storm of factors revolutionising the technology business from top to bottom,” says Rupert Baines, UltraSoC’s chief executive, of the changes he has seen and that have led to his company opening a new engineering and innovation centre in Bristol. “For those of us focused on the semiconductor industry, we’re seeing a move away from the established single-vendor hegemony towards a much more open and almost ‘democratic’ design model.

“This is exemplified by the RISC-V initiative, in which UltraSoC plays a leading role. At the same time, our technology, embedded deep in silicon chips and unseen by the wider world, answers many of the broader questions facing tech companies today. We are moving ‘beyond the chip.'”

The Bristol campus will be headed by Blu Wireless, Nvidia, and Icera alumnus Marcin Hlond. The company has not yet announced a date for the facility’s opening.

Another company singing RISC-V’s praises is Segger, which has recently announced SiFive RISC-V RV32 Coreplex core support in its J-Link debug probe.

“RISC-V is a great CPU architecture. With various open-source and commercial implementations, we believe that it will become very popular, very fast,” claims Alex Grüner, J-Link product manager and chief technical officer at Segger, of the architecture’s potential. “J-Link’s family of professional debug probes are now available to help contribute to and build on the success of RISC-V.”

“The fact that Segger is seeing commercial demand for RISC-V is evidence that open-source semiconductors are enabling a new wave of silicon design,” adds Rick O’Connor, RISC-V Foundation chair. “SiFive and others implementing RISC-V cores based on SiFive’s Coreplex IP will now have the necessary tools to simplify their development workflow.”

The Coreplex support has been introduced via firmware update into all current J-Link models, the company has confirmed, including the low-cost J-Link Edu variant.

The RISC-V Foundation itself, meanwhile, has extended the submission deadline for papers to be entered into its 7th RISC-V Workshop, giving those interested but running late until Sunday to submit their abstracts.

Those interested in presenting a 25 or 12 minute talk to the RISC-V community during the 7th RISC-V Workshop in Milpitas, California on the 28th to the 30th of November now have until Sunday the 24th of September to enter an abstract. Those selected to speak will be notified at the start of October, the Foundation has confirmed.

Applications should be made via the official website.

Andes Technology has contributed a stable and usable LLVM toolchain to the RISC-V community, based on work carried out by Alex Bradbury in the lowRISC project.

“Our contribution includes LLVM, Clang, compiler-rt and a build script just like the one in riscv-gnu-toolchain,” explains Andes’ Kito Cheng of the contribution. “[The] LLVM part is based on Alex’s version. We thank Alex for bringing a great infrastructure to start the RISC-V port. Our version has passed several test suites at all optimisation levels for RV32IMAC and RV64IMAC elf/newlib LLVM toolchain. With this contribution, we hope to accelerate the RISC-V LLVM development, and avoid duplicated work from different implementations/teams.”

At present, Kito explains, the LLVM/Clang toolchain is fully functional for the RV32E, RV32IMC, and RV64IMC architectures, compiler-rt is “a work in progress,” and only the ELF compilation toolchain is presently supported. The toolchain is available from Andes’ GitHub repository now.

Speaking of GitHub, the collaborative version control site has launched two new software packages: Atom-IDE and GitHub Desktop 1.0.

Built following a move to the Electron framework, GitHub Desktop is designed to provide what is described as “a simpler, more unified experience.” New features, in testing since May, include neat means of handling the display of changes between images, faster cloning through parallel asset download, and full integration with existing desktop software. At present, however, the software is only available on Windows and macOS platforms.

Atom-IDE, meanwhile, represents a collaboration with Facebook designed to bring full integrated development environment (IDE) functionality to the popular Atom text editor. The plugins include support for C#, Flow, Java, JavaScript, PHP, and TypeScript with full code- and project-level syntactical analysis functionality. Unlike GitHub Desktop, Atom-IDE is fully cross-platform.

The Linux Foundation has released the 2017 Open Source Jobs Report, and the news is good: demand for full-time open-source workers has risen by more than ten percent year-on-year.

In the survey, which canvassed the opinions of 280 hiring managers from global businesses and 1,800 open-source professionals, 60 percent of companies reported they were actively looking for full-time open-source staff, up from 53 percent last year. The demand, it seems, is outstripping supply: 89 percent of hiring managers surveyed claimed it is difficult to find the right type of talent, up from 87 percent last year, with 73 percent specifically pointing to open-source developers as a gap requiring filling.

The full report is available for download from The Linux Foundation now.

The LoRaWAN Alliance has grown a member stronger this month with the news that open-source focused cloud platform provider Runtime has joined.

“Open, low-power wireless standards are critical in driving the deployment of large scale IoT [Internet of Things] networks,” claims Runtime co-founder and chief technology officer Sterling Hughes of his company’s support for the LoRaWAN standard. “At Runtime, we commercially support an open-source Bluetooth stack because we believe in the Bluetooth SIG’s 30,000 member ecosystem and their approach to developing interoperable solutions. We believe LoRaWAN can have a similar impact in the long range connectivity space, providing inexpensive, ubiquitous backhaul for industrial Bluetooth and Bluetooth Mesh sensor networks.”

“The IIoT [Industrial Internet of Things] alone will add $14.2 trillion to the global economy by the year 2030,” adds co-founder and chief executive officer James Pace. “The critical pieces are coming together to enable very large scale deployments that include the distribution of millions of sensors. LoRaWAN offers a low-cost connectivity choice that enables massive scale deployments; designing connected devices using a foundational open source project such as Apache Mynewt provides IoT companies with a tested open source platform for developing connected sensors.”

Researchers at the University of Washington agree on the need for low-cost and low-power scalable communication standards, and have a suggestion of their own: a LoRa backscatter system capable of running at incredibly low power draws (PDF warning).

“This paper overturns this conventional wisdom about backscatter and presents the first wide-area backscatter system,” researchers Vamsi Talla, Mehrdad Hessar, Bryce Kellogg, Ali Najafi, Joshua R. Smith, and Shyamanth Gollakota wrote in the recently-published paper. “Our design can successfully backscatter from any location between an RF source and receiver, separated by 475m, while being compatible with commodity LoRa hardware. Further, when our backscatter device is co-located with the RF source, the receiver can be as far as 2.8km away.”

The result of the team’s work is a long-range, highly-scalable communications network using ultra-low-cost LoRa compatible integrated circuits – “less than a dime at scale,” the team claim – drawing less than a thousandth of the normal power of an active LoRa radio chipset at 9.25µW. The team has not, however, offered a timescale for commercial availability.

Those needing to compare different microcontroller units (MCUs) for their power efficiency will find the Embedded Microprocessor Benchmark Consortium’s (EEMBC’s) publication of ULPMark-PeripheralProfile (ULPMark-PP) benchmark results of considerable interest.

“The ULPMark working group has done the near-impossible in delivering this highly-beneficial benchmark, but a benchmark without benchmark results is like an electric car without electricity to charge it,” explains Markus Levy, EEMBC president, of the release. “The initial ULPMark-PP results indicate that there is a huge efficiency difference between microcontrollers. Furthermore, these results also highlight the benefits of running at 1.8-2.0 volts versus 3.0 volts. Beyond this, I encourage all embedded system developers to encourage their MCU vendors to publish the results for their devices. A comprehensive table of ULPMark-PP results significantly adds credibility and real-world comparability to the specifications in datasheets.”

Designed to complement the ULPMark-CoreProfile (ULPMark-CP), ULPMark-PP aims to test the efficiency of a microcontroller’s peripheral functions: analogue-to-digital conversion (ADC), real-time clock (RTC), serial peripheral interface (SPI), and pulse-width modulation (PWM). Results from the benchmark are available for public viewing on the official website now. The benchmark itself, however, is only available to licensees and EEMBC members.

Finally, anyone looking for a career boost should check out the new posts available at Embecosm and lowRISC for compiler engineers and hardware engineers respectively.

Embecosm is seeking compiler engineers at its Lymington head office, with remote work a possibility following an initial on-site period. Up to 10 percent of a successful applicant’s time will be allocated for personal projects, and previous experience is not a priority: “What you must be is provably an outstanding programmer (language does not matter),” explains Embecosm’s Judith Jones, “with a commitment to free and open source software.”

lowRISC, meanwhile, is looking for a hardware engineer to work on the development of its eponymous open-source system-on-chip. “lowRISC is an ambitious project with a small core team, so you will be heavily involved in the project’s development direction,” explains lowRISC’s Alex Bradbury. “This role will involve frequent work with external contributors and collaborators. While much of the work will be at the hardware level the post will offer experience of the full hardware/software stack, higher-level simulation tools and architectural design issues.”

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