Calderdale's LoRaWAN Gateway

CRU: LoRaWAN fun, RISC-V education, FPGAs, and more

AB Open’s Andrew Back has written of our work on a LoRaWAN gateway for the region, installed on an iconic 275-feet tall landmark with intermittent power.

Part of AB Open’s participation in the IoTUK Boost programme, the installation is designed to provide connectivity to The Things Network’s long-range radio wide-area network (LoRaWAN) as Things Calderdale. Covering the largest area naturally requires good line-of-site, hence the selection of the iconic Wainhouse Tower. It’s the world’s largest folly, from which excellent views are afforded, but which receives power for as little as three hours a day to run the architectural lighting – a problem solved through the use of a sealed lead-acid battery and charging system.

“Now that the Boost gateway is live we will be turning our attention to supporting the Boost participants in making good use of this,” said Andrew of the work. “Of course, since it’s connected to The Things Network, it’s also open for use by any other members of TTN community and any questions should be directed to the Calderdale Community category on The Things Network forums. Finally, I’d just like to say a huge thanks to everyone at Calderdale Council who have generously given their time in supporting this initiative, and to RS Components for sponsoring the power solution for the gateway install and providing expert advice.”

Anyone interested in the educational aspects of the RISC-V open-source instruction set architecture should subscribe to the new riscv-teach mailing list, which carries academic discussions rather than hardware or software details.

“Education was a primary motivation behind the RISC-V project. This simple high-quality unencumbered ISA, now with its plethora of open-source implementations, should enable the community to collaborate and quickly produce the richest collection of computer architecture educational material ever assembled,” claimed SiFive’s Krste Asanovic in his introduction to the newly-launched list. “Not only can students learn with real cores, but they can also learn to build their own cores and use them directly in their own commercial projects. In Yunsup [Lee]’s words, for the first time: ‘what you learn, is what you use.'”

An archive of the mailing list is available on Google Groups, alongside the existing mailing lists including those targeting hardware and software developers.

As well as launching the new mailing list, Krste Asanovic has given an interview on how RISC-V could revolutionise the semiconductor industry to the Circuit Cellar website.

During the interview, Krste argued that RISC-V could offer a solution to the potential end to Moore’s Law – an observation by Intel co-founder Gordon Moore, noting that the number of transistors which can be fitted to a semiconductor doubles roughly every 18 months without increasing its price, and which has become a mantra for the industry. “The semiconductor industry is in this perfect storm where we see that Moore’s Law is ending and that new technologies and developments are getting more and more expensive,” he told the site. “There are fewer and fewer companies capable of pulling off a new design and making money out of it.

“At the same time there is a growth in demand for custom chips. Everybody is talking about the Internet of Things and all those devices will need a processor—and that cannot be the same processor for all solutions. There will be a growth in silicon products, but that growth will be in many fragmented markets. The old semiconductor business model—having one design and selling many millions of it— doesn’t work anymore. That has worked with the traditional computer and mobile phone markets, but the future will see perhaps hundreds of designs in lower volumes.”

Software developers targeting the RISC-V architecture can now use Matt Godbolt’s Compiler Explorer, thanks to the work of Michael Clark in setting the service up on a Google Cloud instance.

Designed to offer a live, line-by-line and interactive compilation of source code with the results immediately visible in the next window. Michael’s variant of Matt’s work adds an experimental musl-riscv GCC 7.1.0 toolchain, giving it the ability to compile for and demonstrate the output of compilation to riscv32 (32-bit) and riscv64 (64-bit) architectures alongside x86-32 and x86-64. Any valid code entered into the left-hand window will update the output on the right – a valuable tool for debugging and educational use.

“We can use it in the meantime until Matt sets up some riscv toolchains (newlib, gcc) on godbolt.org,” Michael explained of his work. “It would be kinda nice to have on the riscv.org domain although it likely needs to be sandboxed from other apps.” The modified Compiler Explorer is live now.

Hackaday’s Al Williams has written of VexRiscv, a modular RISC-V implementation for field-programmable gate arrays (FPGAs) written in the SpinalHDL hardware definition language.

“This open implementation offers you an easy way to leverage some great tools,” writes Al of the project. “There’s a debugging interface for GDB and a FreeRTOS port. You have a 32-bit part that can achieve 1.16 Dhrystone MIPS/MHz even with all features turned on. This is comparable to commercial 32-bit processors. The documentation is good, too. You can simulate the CPU on a Linux system. There are implementation numbers for some common FPGAs, too. For example, a Cyclone V chip can support 115 MHz to 187 MHz, depending on options. Even a Cyclone II can run a bare-bones version at 156 MHz or a tricked out version at 92 MHz.”

The riscv32-based VexRiscv is available on GitHub now, under an unspecified licence.

FPGA users are likely to also find Jim Lewis’ write-up on improving VHDL for Semi Engineering to be of considerable interest, covering the new VHDL-2017 plus Open Source VHDL Verification Methodology standards.

“If you are using VHDL, there is no compelling reason to use SystemVerilog,” Jim writes while summarising the work of the IEEE 1067 VHDL Working Group. “With my focus on testbenches and OSVVM, my favourite additions are: Interfaces; Arrays of protected types; Pointers to protected types; Shared variables on entity interfaces; Generics on protected types; Instances of generic protected types in a shared variable declaration; Assert API.

“You are probably wondering why standards take so much time,” Jim adds. “VHDL standards are run by volunteers. Time is based on the number of volunteers and the amount of time they donate. We are always looking for a few more talented VHDL design, verification, compiler, and/or LRM experts to help out. If you have one of these skills and want to help, you can find us at EDAwiki.

Lars Lydersen has written for EDN Network on the topic of wireless IoT protocols and their security tradeoffs, offering a valuable primer for anyone looking to implement wireless communications in their next project.

“In the race for time-to-market in the Internet of Things (IoT), proper security is inconvenient because it adds development and component cost and design complexity,” Lars argues. “While many traditional industries have not been exposed to security issues, they suddenly become hacking targets when their products become smart and connected. The issue is that bad press and major security and privacy issues might slow down the adoption of IoT for improving our lives.”

Lars’ write-up includes a look at commissioning schemes for a variety of communication technologies, from Wi-Fi and Bluetooth Low Energy to Zigbee and Thread, and how cryptographic signatures and encryption can be applied to keep communications private and users safe from abuse.

Those who are investigating communications technologies should take a look at the newly-announced Bluetooth Mesh standard, which adds peer-to-peer mesh networking capabilities to Bluetooth Low Energy (BLE).

“By adding support for mesh networking, the Bluetooth member community is continuing a long history of focused innovation to help new, up-and-coming markets flourish,” says Mark Powell, executive director for Bluetooth SIG, of the latest standard. “In the same way the connected device market experienced rapid growth after the introduction of Bluetooth Low Energy, we believe Bluetooth mesh networking can play a vital role in helping early stage markets, such as building automation and wireless sensor networks, experience more rapid growth.”

The Bluetooth Low Energy Mesh standard, its creators have claimed, scales to large-scale networks in industrial and urban settings some thousands of devices large. The standard can also be applied retroactively to existing Bluetooth Low Energy hardware through a firmware update, the Bluetooth SIG has confirmed, though this depends on the device in question having enough memory free on the Bluetooth module to support the functionality.

Meanwhile, US company Hologram has announced the launch of a free tier for its IoT-focused cellular network, offering 1MB of data across 2G-4G networks belonging to more than 300 worldwide carriers.

“At Hologram, we believe cellular connectivity is the future of ubiquitous, secure IoT communication,” writes Ben Forgan of his company’s approach to wide-area networking. “Unfortunately, up until now, cellular connectivity for IoT has been riddled with high barriers to entry. As one of the largest software-defined cellular networks for IoT, Hologram is on a mission to remove these barriers. Today I’m stoked to share the latest barrier we’re removing, the barrier of easy, risk-free access to our global cellular network.”

Under the Developer Plan, users can transmit and receive 1MB – around 1,500 messages – of data per month across 2G, 3G, and 4G networks belonging to more than 300 carriers globally. “The Developer Plan is for every analogue, embedded, and software engineer interested in IoT,” claims Ben. “Our hope is to build a community of developers ready to test the limits and push the boundaries of what’s capable today, to build the tools of tomorrow.”

IoT-focused community group Hardware Pioneers is running a free event on bringing an IoT product to market this August at Cocoon Networks in London.

Featuring speakers from Microchip Technology, Cypress Semiconductor, and Foxconn affiliate Koobe, the free event promises to cover topics from the importance of authentication in LoRaWAN networks and challenges faced when taking an IoT project into production to a talk from Koobe’s Josh Liu, director of operation and entrepreneurship, on working with Taiwanese manufacturing giant Foxconn.

The event is scheduled for the 10th of August, and free tickets are available from the website now.

Finally, Andrew has been interviewed on the Book of the Future podcast (auto-play audio warning) on the topic of global collaboration, the benefits of open source, and RISC-V and related technologies.

During the interview with Book of the Future host Tom Cheesewright, Andrew peers into the future and discusses how collaboration under permissive licence can solve real-world problems, as well as highlighting the various benefits of the RISC-V and other open silicon projects of which regular Community Round-Up readers will be only too aware.

There’s also discussion of the Wuthering Bytes festival, taking place in Hebden Bridge from the 1st to the 10th of September, with a particular focus on the three-day ORConf open-source digital design and embedded systems conference – details of which are available from the official website and free registration for which is open now with AB Open CRU readers cordially invited to attend.

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