1Bitsy Boards on Panels

Community Round-Up: ARM Dev Tools, Five-Network IoT, 128-bit RISC-V, Choosing an RTOS, and an Osmocom CFP

Technology journalist Gareth Halfacree is running the AB Open Community Round-Up series, offering a fortnightly glimpse at what’s happening in and around open source hardware and software, wireless and related topics.

Piotr Esden-Tempski has successfully completed a crowdfunding campaign for the 1Bitsy development board and Black Magic v2.1 JTAG/SWD probe, both of which are being developed and released under a permissive open hardware licence.

The Black Magic v2.1 builds on earlier designs to offer powerful JTAG and SWD programming and debugging capabilities in a compact form factor. The 1Bitsy acts as a companion development device, offering an STM32 processor with an ARM Cortex-M4 core running at 168MHz, 192KB of RAM, and 1MB of flash storage, alongside hardware floating-point and digital signal processing capabilities.

The first 1Bitsy and Black Magic boards are expected to reach backers of the campaign beginning February 2017. Pre-orders and links to the GitHub repositories for both devices can be found on the official website.

Pycom has also enjoyed success with its own crowdfunding campaign for the FiPy, which is claimed to be the world’s first Internet of Things (IoT) centric development board boasting support for five distinct wireless networking standards.

The FiPy, built with development in MicroPython in mind, includes a radio module which provides connectivity to Wi-Fi, Long Term Evolution (LTE), Sigfox, Bluetooth, and LoRa networks, all in the same footprint as the company’s previous Wi-Fi- and LoRa-based WiPy and LoPy boards. Any and all of the networks may be used at the same time, including full support for switching between networks on demand. The first boards are expected to ship in April 2017, with more information available from the company’s official product page.

Noted developer Fabrice Bellard has released RISCVEMU, the first publicly-available RISC-V system emulator boasting 32-, 64-, and 128-bit support for both addressing and floating-point calculation purposes, complete with a JavaScript demo booting into 64-bit Linux.

Based on the open RV128IMAFDQC instruction set architecture (ISA), the release of RISCVEMU has driven considerable discussion among the members of the RISC-V software developers mailing list (SW Dev) as to the need to develop a 128-bit toolchain to take advantage of the new 128-bit support Fabrice’s emulator brings to the RISC-V community. The emulator itself, which has no external dependencies, is released under the permissive MIT Licence.

Those currently in the process of planning an embedded project may find Mentor Graphics’ recent white paper on choosing a real-time operating system (RTOS) a handy resource, even if you haven’t decided whether you actually need an RTOS in the first place.

Split into what the company describes as the five key issues the white paper looks at whether you need an operating system at all, whether that operating system should be hard real time or more flexible, warnings about the drawbacks of custom implementations, how to compare performance between OSes, and considerations regarding OS selection and implementation on multi-core platforms.

Finally, sysmocom’s Harald Welte gave a cellular network security talk at the 33rd Annual Chaos Communication Congress (33C3), including the announcement of an initiative offering free Osmocom nano3G femtocell devices in an effort to encourage developers to join the work towards developing a stable and high-performance platform for open 3G/3.5G cellular networking.

Running through to the 31st of January, the call for participation is open to any suitably skilled member of the public and comes with the promise from sysmocom to provide 50 free nano3G femtocells and five SIM cards to successful individuals and non-commercial research institutions willing to help accelerate the development of Osmocom’s 3.5G implementation, improve the documentation, or use Osmocom in their own research projects.

Interested parties should email their proposal to accelerate3g5@sysmocom.de, with more information available from Andrew Back’s write-up over on RS DesignSpark.




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